| Message ID | 1635847013-3220-2-git-send-email-tdas@codeaurora.org (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Add support for LPASS Core and Audio Clock for SC7280 | expand |
Quoting Taniya Das (2021-11-02 02:56:50) > PLL poll for lock detection can take more than 100us for certain type What types of PLLs? Is this fixing something that's broken? Or fixing a future problem? > of PLLs, thus update to 200us. > Does it needs a Fixes tag? > Signed-off-by: Taniya Das <tdas@codeaurora.org> > --- > drivers/clk/qcom/clk-alpha-pll.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c > index eaedcce..7cf6cfa 100644 > --- a/drivers/clk/qcom/clk-alpha-pll.c > +++ b/drivers/clk/qcom/clk-alpha-pll.c > @@ -204,7 +204,7 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, > if (ret) > return ret; > > - for (count = 100; count > 0; count--) { > + for (count = 200; count > 0; count--) { > ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); > if (ret)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index eaedcce..7cf6cfa 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -204,7 +204,7 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, if (ret) return ret; - for (count = 100; count > 0; count--) { + for (count = 200; count > 0; count--) { ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); if (ret) return ret;
PLL poll for lock detection can take more than 100us for certain type of PLLs, thus update to 200us. Signed-off-by: Taniya Das <tdas@codeaurora.org> --- drivers/clk/qcom/clk-alpha-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.