diff mbox series

drm/i915/: Extend VRR platform support to Gen 11

Message ID 20211116231209.28621-1-manasi.d.navare@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/: Extend VRR platform support to Gen 11 | expand

Commit Message

Navare, Manasi Nov. 16, 2021, 11:12 p.m. UTC
VRR is supported on Gen 11 HW , hence extend the support
in the driver to enable this for Gen 11.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Ville Syrjälä Nov. 17, 2021, 6:27 p.m. UTC | #1
On Tue, Nov 16, 2021 at 03:12:09PM -0800, Manasi Navare wrote:
> VRR is supported on Gen 11 HW , hence extend the support
> in the driver to enable this for Gen 11.

Yeah, based on my testing icl works as well (or as poorly)
as tgl.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 94840af45750..3b00a8edbb1d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1741,7 +1741,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  
>  #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
>  
> -#define HAS_VRR(i915)	(GRAPHICS_VER(i915) >= 12)
> +#define HAS_VRR(i915)	(GRAPHICS_VER(i915) >= 11)
>  
>  #define HAS_ASYNC_FLIPS(i915)		(DISPLAY_VER(i915) >= 5)
>  
> -- 
> 2.19.1
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 94840af45750..3b00a8edbb1d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1741,7 +1741,7 @@  IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
 
-#define HAS_VRR(i915)	(GRAPHICS_VER(i915) >= 12)
+#define HAS_VRR(i915)	(GRAPHICS_VER(i915) >= 11)
 
 #define HAS_ASYNC_FLIPS(i915)		(DISPLAY_VER(i915) >= 5)