| Message ID | 20211118132502.984059-3-lucas.araujo@eldorado.org.br (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Fix mtfsf, mtfsfi and mtfsb1 bug | expand |
On Thu, 18 Nov 2021, Lucas Mateus Castro (alqotel) wrote: > This commit fixes the difference reported in the bug in the reserved > bit 52, it does this by adding this bit to the mask of bits to not be > directly altered in the ppc_store_fpscr function (the hardware used to > compare to QEMU was a Power9). > > Although this is a difference reported in the bug, since it's a reserved > bit it may be a "don't care" case, as put in the bug report. Looking at > the ISA it doesn't explicitly mentions this bit can't be set, like it > does for FEX and VX, so I'm unsure if this is necessary. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/266 > Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> > --- > target/ppc/cpu.c | 2 +- > target/ppc/cpu.h | 3 +++ > 2 files changed, 4 insertions(+), 1 deletion(-) > > diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c > index f933d9f2bd..d7b42bae52 100644 > --- a/target/ppc/cpu.c > +++ b/target/ppc/cpu.c > @@ -112,7 +112,7 @@ static inline void fpscr_set_rounding_mode(CPUPPCState *env) > > void ppc_store_fpscr(CPUPPCState *env, target_ulong val) > { > - val &= ~(FP_VX | FP_FEX); > + val &= FPSCR_MTFS_MASK; > if (val & FPSCR_IX) { > val |= FP_VX; > } > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index e946da5f3a..53463092ab 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -759,6 +759,9 @@ enum { > FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \ > FP_VXSQRT | FP_VXCVI) > > +/* FPSCR bits that can be set by mtfsf, mtfsfi and mtfsb1 */ > +#define FPSCR_MTFS_MASK (~((1ull << 11) | FP_VX | FP_FEX)) Instead of (1ull << 11) maybe PPC_BIT(52) is a bit clearer (or not depending on personal preference, so I don't mind either way. Regards, BALATON Zoltan > + > /*****************************************************************************/ > /* Vector status and control register */ > #define VSCR_NJ 16 /* Vector non-java */ >
On 11/18/21 2:25 PM, Lucas Mateus Castro (alqotel) wrote: > +/* FPSCR bits that can be set by mtfsf, mtfsfi and mtfsb1 */ > +#define FPSCR_MTFS_MASK (~((1ull << 11) | FP_VX | FP_FEX)) If you're going to make the reserved bit 52 read-as-zero-writes-ignored, you should do the same for reserved bits 0-31. Otherwise drop this and let the bits be read-write with no effect. r~
diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c index f933d9f2bd..d7b42bae52 100644 --- a/target/ppc/cpu.c +++ b/target/ppc/cpu.c @@ -112,7 +112,7 @@ static inline void fpscr_set_rounding_mode(CPUPPCState *env) void ppc_store_fpscr(CPUPPCState *env, target_ulong val) { - val &= ~(FP_VX | FP_FEX); + val &= FPSCR_MTFS_MASK; if (val & FPSCR_IX) { val |= FP_VX; } diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index e946da5f3a..53463092ab 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -759,6 +759,9 @@ enum { FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \ FP_VXSQRT | FP_VXCVI) +/* FPSCR bits that can be set by mtfsf, mtfsfi and mtfsb1 */ +#define FPSCR_MTFS_MASK (~((1ull << 11) | FP_VX | FP_FEX)) + /*****************************************************************************/ /* Vector status and control register */ #define VSCR_NJ 16 /* Vector non-java */
This commit fixes the difference reported in the bug in the reserved bit 52, it does this by adding this bit to the mask of bits to not be directly altered in the ppc_store_fpscr function (the hardware used to compare to QEMU was a Power9). Although this is a difference reported in the bug, since it's a reserved bit it may be a "don't care" case, as put in the bug report. Looking at the ISA it doesn't explicitly mentions this bit can't be set, like it does for FEX and VX, so I'm unsure if this is necessary. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/266 Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> --- target/ppc/cpu.c | 2 +- target/ppc/cpu.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-)