[v1,03/12] target/riscv: Implement function kvm_arch_init_vcpu

Commit Message

Yifei Jiang Nov. 20, 2021, 7:46 a.m. UTC

Get isa info from kvm while kvm init.

Signed-off-by: Yifei Jiang <[e-mail]>
Signed-off-by: Mingwang Li <[e-mail]>
Reviewed-by: Alistair Francis <[e-mail]>
---
 target/riscv/kvm.c | 32 +++++++++++++++++++++++++++++++-
 1 file changed, 31 insertions(+), 1 deletion(-)

Comments

Richard Henderson Nov. 20, 2021, 10:19 p.m. UTC | #1

On 11/20/21 8:46 AM, Yifei Jiang wrote:
> +    id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, KVM_REG_RISCV_CONFIG_REG(isa));
> +    ret = kvm_get_one_reg(cs, id, &isa);
> +    if (ret) {
> +        return ret;
> +    }
> +    env->misa_mxl |= isa;

This doesn't look right.
I'm sure you meant

     env->misa_ext = isa;


r~

Yifei Jiang Dec. 10, 2021, 9:55 a.m. UTC | #2

> -----Original Message-----
> From: Richard Henderson [mailto:[e-mail]]
> Sent: Sunday, November 21, 2021 6:19 AM
> To: Jiangyifei <[e-mail]>; [e-mail];
> [e-mail]
> Cc: [e-mail]; limingwang (A) <[e-mail]>;
> [e-mail]; [e-mail]; [e-mail]; wanbo (G)
> <[e-mail]>; Alistair Francis <[e-mail]>;
> [e-mail]; Wanghaibin (D)
> <[e-mail]>; [e-mail]; Fanliang (EulerOS)
> <[e-mail]>; Wubin (H) <[e-mail]>
> Subject: Re: [PATCH v1 03/12] target/riscv: Implement function
> kvm_arch_init_vcpu
> 
> On 11/20/21 8:46 AM, Yifei Jiang wrote:
> > +    id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG,
> KVM_REG_RISCV_CONFIG_REG(isa));
> > +    ret = kvm_get_one_reg(cs, id, &isa);
> > +    if (ret) {
> > +        return ret;
> > +    }
> > +    env->misa_mxl |= isa;
> 
> This doesn't look right.
> I'm sure you meant
> 
>      env->misa_ext = isa;
> 
> 
> r~

Thanks, it will be modified in the next series.

Yifei

Patch

diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 687dd4b621..9f9692fb9e 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -38,6 +38,23 @@ 
 #include "qemu/log.h"
 #include "hw/loader.h"
 
+static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, uint64_t idx)
+{
+    uint64_t id = KVM_REG_RISCV | type | idx;
+
+    switch (riscv_cpu_mxl(env)) {
+    case MXL_RV32:
+        id |= KVM_REG_SIZE_U32;
+        break;
+    case MXL_RV64:
+        id |= KVM_REG_SIZE_U64;
+        break;
+    default:
+        g_assert_not_reached();
+    }
+    return id;
+}
+
 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
     KVM_CAP_LAST_INFO
 };
@@ -79,7 +96,20 @@  void kvm_arch_init_irq_routing(KVMState *s)
 
 int kvm_arch_init_vcpu(CPUState *cs)
 {
-    return 0;
+    int ret = 0;
+    target_ulong isa;
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    CPURISCVState *env = &cpu->env;
+    uint64_t id;
+
+    id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, KVM_REG_RISCV_CONFIG_REG(isa));
+    ret = kvm_get_one_reg(cs, id, &isa);
+    if (ret) {
+        return ret;
+    }
+    env->misa_mxl |= isa;
+
+    return ret;
 }
 
 int kvm_arch_msi_data_to_gsi(uint32_t data)