| Message ID | 20211209205456.11027-2-marten.lindahl@axis.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add ARTPEC-8 support to DWMMC controller | expand |
On Thu, 09 Dec 2021 21:54:53 +0100, Mårten Lindahl wrote: > The ARTPEC-8 SoC has a DWMMC controller that is compatible with the > Exynos 7 version v2.70a. The main differences from Exynos 7 is that it > does not support HS400 and has extended data read timeout. > > Add compatibility string "axis,artpec8-dw-mshc" for ARTPEC-8. > > Signed-off-by: Mårten Lindahl <marten.lindahl@axis.com> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> > --- > > v2: > - Change compatible string vendor prefix > > v3 -> v4: > - Add Krzysztof's Reviewed-by tag > > Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt index 0419a63f73a0..753e9d7d8956 100644 --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt @@ -22,6 +22,8 @@ Required Properties: specific extensions. - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7 specific extensions having an SMU. + - "axis,artpec8-dw-mshc": for controllers with ARTPEC-8 specific + extensions. * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface unit (ciu) clock. This property is applicable only for Exynos5 SoC's and