| Message ID | 20211216051844.3921088-1-vineetg@rivosinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: Enable bitmanip Zb[abcs] instructions | expand |
On Thu, Dec 16, 2021 at 3:21 PM Vineet Gupta <vineetg@rivosinc.com> wrote: > > The bitmanip extension has now been ratified [1] and upstream tooling > (gcc/binutils) support it too, so move them out of experimental and also > enable by default (for better test exposure/coverage) > > [1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions > > Signed-off-by: Vineet Gupta <vineetg@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index f81299812350..c00d59cd04b5 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -635,10 +635,10 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), > > /* These are experimental so mark with 'x-' */ > - DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false), > - DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false), > - DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false), > - DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false), > + DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), > + DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), > + DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), > + DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), > DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), > DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), > DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), > -- > 2.30.2 > >
On Thu, Dec 16, 2021 at 3:21 PM Vineet Gupta <vineetg@rivosinc.com> wrote: > > The bitmanip extension has now been ratified [1] and upstream tooling > (gcc/binutils) support it too, so move them out of experimental and also > enable by default (for better test exposure/coverage) > > [1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions > > Signed-off-by: Vineet Gupta <vineetg@rivosinc.com> Thanks! Applied to riscv-to-apply.next Alistair > --- > target/riscv/cpu.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index f81299812350..c00d59cd04b5 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -635,10 +635,10 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), > > /* These are experimental so mark with 'x-' */ > - DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false), > - DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false), > - DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false), > - DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false), > + DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), > + DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), > + DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), > + DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), > DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), > DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), > DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), > -- > 2.30.2 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f81299812350..c00d59cd04b5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -635,10 +635,10 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), /* These are experimental so mark with 'x-' */ - DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false), - DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false), - DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false), - DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false), + DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), + DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), + DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), + DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
The bitmanip extension has now been ratified [1] and upstream tooling (gcc/binutils) support it too, so move them out of experimental and also enable by default (for better test exposure/coverage) [1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions Signed-off-by: Vineet Gupta <vineetg@rivosinc.com> --- target/riscv/cpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)