| Message ID | 20211221052722.597407-4-yoshihiro.shimoda.uh@renesas.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | treewide: rcar-dmac: Add support for R-Car S4-8 | expand |
> On 12/21/2021 6:27 AM Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: > > > Add SYS-DMAC nodes for r8a779f0. > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > --- > arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 70 +++++++++++++++++++++++ > 1 file changed, 70 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi > index eda597766eaf..5426532d10e2 100644 > --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi > @@ -94,6 +94,76 @@ scif3: serial@e6c50000 { > status = "disabled"; > }; > > + dmac0: dma-controller@e7350000 { > + compatible = "renesas,dmac-r8a779f0", > + "renesas,rcar-gen4-dmac"; > + reg = <0 0xe7350000 0 0x1000>, > + <0 0xe7300000 0 0x10000>; > + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "error", > + "ch0", "ch1", "ch2", "ch3", "ch4", > + "ch5", "ch6", "ch7", "ch8", "ch9", > + "ch10", "ch11", "ch12", "ch13", > + "ch14", "ch15"; > + clocks = <&cpg CPG_MOD 709>; > + clock-names = "fck"; > + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; > + resets = <&cpg 709>; > + #dma-cells = <1>; > + dma-channels = <16>; > + }; > + > + dmac1: dma-controller@e7351000 { > + compatible = "renesas,dmac-r8a779f0", > + "renesas,rcar-gen4-dmac"; > + reg = <0 0xe7351000 0 0x1000>, > + <0 0xe7310000 0 0x10000>; > + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "error", > + "ch0", "ch1", "ch2", "ch3", "ch4", > + "ch5", "ch6", "ch7", "ch8", "ch9", > + "ch10", "ch11", "ch12", "ch13", > + "ch14", "ch15"; > + clocks = <&cpg CPG_MOD 710>; > + clock-names = "fck"; > + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; > + resets = <&cpg 710>; > + #dma-cells = <1>; > + dma-channels = <16>; > + }; > + > gic: interrupt-controller@f1000000 { > compatible = "arm,gic-v3"; > #interrupt-cells = <3>; > -- > 2.25.1 Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu> CU Uli
On Tue, Dec 21, 2021 at 10:50 AM Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: > Add SYS-DMAC nodes for r8a779f0. > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v5.18. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index eda597766eaf..5426532d10e2 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -94,6 +94,76 @@ scif3: serial@e6c50000 { status = "disabled"; }; + dmac0: dma-controller@e7350000 { + compatible = "renesas,dmac-r8a779f0", + "renesas,rcar-gen4-dmac"; + reg = <0 0xe7350000 0 0x1000>, + <0 0xe7300000 0 0x10000>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", "ch4", + "ch5", "ch6", "ch7", "ch8", "ch9", + "ch10", "ch11", "ch12", "ch13", + "ch14", "ch15"; + clocks = <&cpg CPG_MOD 709>; + clock-names = "fck"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 709>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + dmac1: dma-controller@e7351000 { + compatible = "renesas,dmac-r8a779f0", + "renesas,rcar-gen4-dmac"; + reg = <0 0xe7351000 0 0x1000>, + <0 0xe7310000 0 0x10000>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", "ch4", + "ch5", "ch6", "ch7", "ch8", "ch9", + "ch10", "ch11", "ch12", "ch13", + "ch14", "ch15"; + clocks = <&cpg CPG_MOD 710>; + clock-names = "fck"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 710>; + #dma-cells = <1>; + dma-channels = <16>; + }; + gic: interrupt-controller@f1000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>;
Add SYS-DMAC nodes for r8a779f0. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 70 +++++++++++++++++++++++ 1 file changed, 70 insertions(+)