| Message ID | 20211129153330.37719-8-nbd@nbd.name (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add support for Airoha EN7523 SoC | expand |
Hi Felix,
I love your patch! Perhaps something to improve:
[auto build test WARNING on robh/for-next]
[also build test WARNING on clk/clk-next v5.16-rc3 next-20211202]
[cannot apply to linusw-gpio/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Felix-Fietkau/dt-bindings-Add-vendor-prefix-for-Airoha/20211130-033938
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: mips-randconfig-s031-20211202 (https://download.01.org/0day-ci/archive/20211203/202112030121.BuKKR1T4-lkp@intel.com/config)
compiler: mips64-linux-gcc (GCC) 11.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.4-dirty
# https://github.com/0day-ci/linux/commit/f1c5b70976ce5352c8ac2ae85739e1be63f59ec2
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Felix-Fietkau/dt-bindings-Add-vendor-prefix-for-Airoha/20211130-033938
git checkout f1c5b70976ce5352c8ac2ae85739e1be63f59ec2
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=mips SHELL=/bin/bash drivers/clk/ drivers/gpio/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
sparse warnings: (new ones prefixed by >>)
command-line: note: in included file:
builtin:1:9: sparse: sparse: preprocessor token __ATOMIC_ACQUIRE redefined
builtin:0:0: sparse: this was the original definition
builtin:1:9: sparse: sparse: preprocessor token __ATOMIC_SEQ_CST redefined
builtin:0:0: sparse: this was the original definition
builtin:1:9: sparse: sparse: preprocessor token __ATOMIC_ACQ_REL redefined
builtin:0:0: sparse: this was the original definition
builtin:1:9: sparse: sparse: preprocessor token __ATOMIC_RELEASE redefined
builtin:0:0: sparse: this was the original definition
drivers/clk/clk-en7523.c:202:27: sparse: sparse: incorrect type in initializer (different address spaces) @@ expected void *np_base @@ got void [noderef] __iomem *base @@
drivers/clk/clk-en7523.c:202:27: sparse: expected void *np_base
drivers/clk/clk-en7523.c:202:27: sparse: got void [noderef] __iomem *base
>> drivers/clk/clk-en7523.c:206:29: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got void * @@
drivers/clk/clk-en7523.c:206:29: sparse: expected void const volatile [noderef] __iomem *mem
drivers/clk/clk-en7523.c:206:29: sparse: got void *
>> drivers/clk/clk-en7523.c:208:29: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got void * @@
drivers/clk/clk-en7523.c:208:29: sparse: expected void volatile [noderef] __iomem *mem
drivers/clk/clk-en7523.c:208:29: sparse: got void *
drivers/clk/clk-en7523.c:213:29: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got void * @@
drivers/clk/clk-en7523.c:213:29: sparse: expected void volatile [noderef] __iomem *mem
drivers/clk/clk-en7523.c:213:29: sparse: got void *
drivers/clk/clk-en7523.c:217:29: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got void * @@
drivers/clk/clk-en7523.c:217:29: sparse: expected void const volatile [noderef] __iomem *mem
drivers/clk/clk-en7523.c:217:29: sparse: got void *
drivers/clk/clk-en7523.c:220:37: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got void * @@
drivers/clk/clk-en7523.c:220:37: sparse: expected void volatile [noderef] __iomem *mem
drivers/clk/clk-en7523.c:220:37: sparse: got void *
drivers/clk/clk-en7523.c:222:36: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got void * @@
drivers/clk/clk-en7523.c:222:36: sparse: expected void volatile [noderef] __iomem *mem
drivers/clk/clk-en7523.c:222:36: sparse: got void *
drivers/clk/clk-en7523.c:224:37: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got void * @@
drivers/clk/clk-en7523.c:224:37: sparse: expected void volatile [noderef] __iomem *mem
drivers/clk/clk-en7523.c:224:37: sparse: got void *
drivers/clk/clk-en7523.c:229:29: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got void * @@
drivers/clk/clk-en7523.c:229:29: sparse: expected void const volatile [noderef] __iomem *mem
drivers/clk/clk-en7523.c:229:29: sparse: got void *
drivers/clk/clk-en7523.c:230:37: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got void * @@
drivers/clk/clk-en7523.c:230:37: sparse: expected void volatile [noderef] __iomem *mem
drivers/clk/clk-en7523.c:230:37: sparse: got void *
drivers/clk/clk-en7523.c:232:36: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got void * @@
drivers/clk/clk-en7523.c:232:36: sparse: expected void volatile [noderef] __iomem *mem
drivers/clk/clk-en7523.c:232:36: sparse: got void *
drivers/clk/clk-en7523.c:241:27: sparse: sparse: incorrect type in initializer (different address spaces) @@ expected void *np_base @@ got void [noderef] __iomem *base @@
drivers/clk/clk-en7523.c:241:27: sparse: expected void *np_base
drivers/clk/clk-en7523.c:241:27: sparse: got void [noderef] __iomem *base
drivers/clk/clk-en7523.c:244:29: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got void * @@
drivers/clk/clk-en7523.c:244:29: sparse: expected void const volatile [noderef] __iomem *mem
drivers/clk/clk-en7523.c:244:29: sparse: got void *
drivers/clk/clk-en7523.c:246:29: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got void * @@
drivers/clk/clk-en7523.c:246:29: sparse: expected void volatile [noderef] __iomem *mem
drivers/clk/clk-en7523.c:246:29: sparse: got void *
vim +206 drivers/clk/clk-en7523.c
198
199 static int en7523_pci_enable(struct clk_hw *hw)
200 {
201 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
202 void *np_base = cg->base;
203 u32 val, mask;
204
205 /* Need to pull device low before reset */
> 206 val = readl(np_base + REG_PCI_CONTROL);
207 val &= ~(REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT);
> 208 writel(val, np_base + REG_PCI_CONTROL);
209 usleep_range(1000, 2000);
210
211 /* Enable PCIe port 1 */
212 val |= REG_PCI_CONTROL_REFCLK_EN1;
213 writel(val, np_base + REG_PCI_CONTROL);
214 usleep_range(1000, 2000);
215
216 /* Reset to default */
217 val = readl(np_base + REG_RESET_CONTROL);
218 mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 |
219 REG_RESET_CONTROL_PCIEHB;
220 writel(val & ~mask, np_base + REG_RESET_CONTROL);
221 usleep_range(1000, 2000);
222 writel(val | mask, np_base + REG_RESET_CONTROL);
223 msleep(100);
224 writel(val & ~mask, np_base + REG_RESET_CONTROL);
225 usleep_range(5000, 10000);
226
227 /* Release device */
228 mask = REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT;
229 val = readl(np_base + REG_PCI_CONTROL);
230 writel(val & ~mask, np_base + REG_PCI_CONTROL);
231 usleep_range(1000, 2000);
232 writel(val | mask, np_base + REG_PCI_CONTROL);
233 msleep(250);
234
235 return 0;
236 }
237
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
Quoting Felix Fietkau (2021-11-29 07:33:23) > This driver only registers fixed rate clocks, since the clocks are fully > initialized by the boot loader and should not be changed later, according > to Airoha. > > Signed-off-by: Felix Fietkau <nbd@nbd.name> > --- > arch/arm/boot/dts/en7523.dtsi | 8 + > drivers/clk/Kconfig | 9 + > drivers/clk/Makefile | 1 + > drivers/clk/clk-en7523.c | 356 ++++++++++++++++++++++++++++++++++ > 4 files changed, 374 insertions(+) > create mode 100644 drivers/clk/clk-en7523.c Pleas don't mix clk driver changes and dts file updates together. Instead, introduce the clk driver in one patch and add the dts node in another patch so that the different maintainers can pick up the patch for the area they maintain. > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig > index c5b3dc97396a..b542f58c58d2 100644 > --- a/drivers/clk/Kconfig > +++ b/drivers/clk/Kconfig > @@ -192,6 +192,15 @@ config COMMON_CLK_CS2000_CP > help > If you say yes here you get support for the CS2000 clock multiplier. > > +config COMMON_CLK_EN7523 > + bool "Clock driver for Airoha EN7523 SoC system clocks" > + depends on OF > + depends on ARCH_AIROHA || ARM || COMPILE_TEST Is this supposed to have parenthesis somewhere? Why is depending on ARM useful? > + default ARCH_AIROHA > + help > + This driver provides the fixed clocks and gates present on Airoha > + ARM silicon. > + > config COMMON_CLK_FSL_FLEXSPI > tristate "Clock driver for FlexSPI on Layerscape SoCs" > depends on ARCH_LAYERSCAPE || COMPILE_TEST > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile > index e42312121e51..be11d88c1603 100644 > --- a/drivers/clk/Makefile > +++ b/drivers/clk/Makefile > @@ -27,6 +27,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o > obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o > obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o > obj-$(CONFIG_ARCH_SPARX5) += clk-sparx5.o > +obj-$(CONFIG_COMMON_CLK_EN7523) += clk-en7523.o > obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o > obj-$(CONFIG_COMMON_CLK_FSL_FLEXSPI) += clk-fsl-flexspi.o > obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o > diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c > new file mode 100644 > index 000000000000..f1774a5bf537 > --- /dev/null > +++ b/drivers/clk/clk-en7523.c > @@ -0,0 +1,356 @@ > +// SPDX-License-Identifier: GPL-2.0-only > + > +#include <linux/regmap.h> > +#include <linux/clk-provider.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > +#include <dt-bindings/clock/en7523-clk.h> > +#include <linux/clk.h> Is this include used? > + > +#define REG_PCI_CONTROL 0x88 > +#define REG_PCI_CONTROL_PERSTOUT BIT(29) > +#define REG_PCI_CONTROL_PERSTOUT1 BIT(26) > +#define REG_PCI_CONTROL_REFCLK_EN1 BIT(22) > +#define REG_GSW_CLK_DIV_SEL 0x1b4 [...] > + > +static struct clk *en7523_register_pcie_clk(struct device *dev, > + void __iomem *np_base) > +{ > + static const struct clk_ops pcie_gate_ops = { > + .is_enabled = en7523_pci_is_enabled, > + .enable = en7523_pci_enable, > + .disable = en7523_pci_disable, > + }; > + struct clk_init_data init = { > + .name = "pcie", > + .ops = &pcie_gate_ops, > + }; > + struct en_clk_gate *cg; > + struct clk *clk; > + > + cg = devm_kzalloc(dev, sizeof(*cg), GFP_KERNEL); > + if (!cg) > + return NULL; > + > + cg->base = np_base; > + cg->hw.init = &init; > + en7523_pci_disable(&cg->hw); > + > + clk = clk_register(NULL, &cg->hw); Please use clk_hw_register > + if (IS_ERR(clk)) > + clk = NULL; > + > + return clk; > +} > + > +static void en7523_register_clocks(struct device *dev, struct clk_onecell_data *clk_data, > + void __iomem *base, void __iomem *np_base) > +{ > + struct clk *clk; > + u32 rate; > + int i; > + > + for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) { > + const struct en_clk_desc *desc = &en7523_base_clks[i]; > + > + rate = en7523_get_base_rate(base, i); > + rate /= en7523_get_div(base, i); > + > + clk = clk_register_fixed_rate(NULL, desc->name, NULL, 0, rate); > + if (IS_ERR(clk)) { > + pr_err("Failed to register clk %s: %ld\n", > + desc->name, PTR_ERR(clk)); > + continue; > + } > + > + clk_data->clks[desc->id] = clk; > + } > + > + clk = en7523_register_pcie_clk(dev, np_base); > + clk_data->clks[EN7523_CLK_PCIE] = clk; > + > + clk_data->clk_num = EN7523_NUM_CLOCKS; > +} > + > +static int en7523_clk_probe(struct platform_device *pdev) > +{ > + struct device_node *node = pdev->dev.of_node; > + struct clk_onecell_data *clk_data; > + void __iomem *base, *np_base; > + int r; > + > + base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(base)) > + return PTR_ERR(base); > + > + np_base = devm_platform_ioremap_resource(pdev, 1); > + if (IS_ERR(base)) > + return PTR_ERR(np_base); > + > + clk_data = devm_kzalloc(&pdev->dev, sizeof(*clk_data), GFP_KERNEL); > + if (!clk_data) > + return -ENOMEM; > + > + clk_data->clks = devm_kcalloc(&pdev->dev, EN7523_NUM_CLOCKS, > + sizeof(*clk_data->clks), GFP_KERNEL); > + if (!clk_data->clks) > + return -ENOMEM; > + > + en7523_register_clocks(&pdev->dev, clk_data, base, np_base); > + > + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); Please add a clk_hw provider instead of a clk provider. > + if (r)
diff --git a/arch/arm/boot/dts/en7523.dtsi b/arch/arm/boot/dts/en7523.dtsi index 7e17311a3f90..0148958c607b 100644 --- a/arch/arm/boot/dts/en7523.dtsi +++ b/arch/arm/boot/dts/en7523.dtsi @@ -2,6 +2,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/en7523-clk.h> / { interrupt-parent = <&gic>; @@ -82,6 +83,13 @@ L2_0: l2-cache0 { }; }; + scu: scu@1fa20000 { + compatible = "airoha,en7523-scu"; + reg = <0x1fa20000 0x400>, + <0x1fb00000 0x1000>; + #clock-cells = <1>; + }; + gic: interrupt-controller@9000000 { compatible = "arm,gic-v3"; interrupt-controller; diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index c5b3dc97396a..b542f58c58d2 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -192,6 +192,15 @@ config COMMON_CLK_CS2000_CP help If you say yes here you get support for the CS2000 clock multiplier. +config COMMON_CLK_EN7523 + bool "Clock driver for Airoha EN7523 SoC system clocks" + depends on OF + depends on ARCH_AIROHA || ARM || COMPILE_TEST + default ARCH_AIROHA + help + This driver provides the fixed clocks and gates present on Airoha + ARM silicon. + config COMMON_CLK_FSL_FLEXSPI tristate "Clock driver for FlexSPI on Layerscape SoCs" depends on ARCH_LAYERSCAPE || COMPILE_TEST diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index e42312121e51..be11d88c1603 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o obj-$(CONFIG_ARCH_SPARX5) += clk-sparx5.o +obj-$(CONFIG_COMMON_CLK_EN7523) += clk-en7523.o obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o obj-$(CONFIG_COMMON_CLK_FSL_FLEXSPI) += clk-fsl-flexspi.o obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c new file mode 100644 index 000000000000..f1774a5bf537 --- /dev/null +++ b/drivers/clk/clk-en7523.c @@ -0,0 +1,356 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <linux/regmap.h> +#include <linux/clk-provider.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <dt-bindings/clock/en7523-clk.h> +#include <linux/clk.h> + +#define REG_PCI_CONTROL 0x88 +#define REG_PCI_CONTROL_PERSTOUT BIT(29) +#define REG_PCI_CONTROL_PERSTOUT1 BIT(26) +#define REG_PCI_CONTROL_REFCLK_EN1 BIT(22) +#define REG_GSW_CLK_DIV_SEL 0x1b4 +#define REG_EMI_CLK_DIV_SEL 0x1b8 +#define REG_BUS_CLK_DIV_SEL 0x1bc +#define REG_SPI_CLK_DIV_SEL 0x1c4 +#define REG_SPI_CLK_FREQ_SEL 0x1c8 +#define REG_NPU_CLK_DIV_SEL 0x1fc +#define REG_CRYPTO_CLKSRC 0x200 +#define REG_RESET_CONTROL 0x834 +#define REG_RESET_CONTROL_PCIEHB BIT(29) +#define REG_RESET_CONTROL_PCIE1 BIT(27) +#define REG_RESET_CONTROL_PCIE2 BIT(26) + +struct en_clk_desc { + int id; + const char *name; + u32 base_reg; + u32 base_bits; + u32 base_shift; + union { + const u32 *base_values; + u32 base_value; + }; + int n_base_values; + + u32 div_reg; + u32 div_bits; + u32 div_shift; + u32 div_val0; + u32 div_step; +}; + +struct en_clk_gate { + void __iomem *base; + struct clk_hw hw; +}; + +static const u32 gsw_base[] = { 400000000, 500000000 }; +static const u32 emi_base[] = { 333000000, 400000000 }; +static const u32 bus_base[] = { 500000000, 540000000 }; +static const u32 slic_base[] = { 100000000, 3125000 }; +static const u32 npu_base[] = { 333000000, 400000000, 500000000 }; + +static const struct en_clk_desc en7523_base_clks[] = { + { + .id = EN7523_CLK_GSW, + .name = "gsw", + + .base_reg = REG_GSW_CLK_DIV_SEL, + .base_bits = 1, + .base_shift = 8, + .base_values = gsw_base, + .n_base_values = ARRAY_SIZE(gsw_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + }, { + .id = EN7523_CLK_EMI, + .name = "emi", + + .base_reg = REG_EMI_CLK_DIV_SEL, + .base_bits = 1, + .base_shift = 8, + .base_values = emi_base, + .n_base_values = ARRAY_SIZE(emi_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + }, { + .id = EN7523_CLK_BUS, + .name = "bus", + + .base_reg = REG_BUS_CLK_DIV_SEL, + .base_bits = 1, + .base_shift = 8, + .base_values = bus_base, + .n_base_values = ARRAY_SIZE(bus_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + }, { + .id = EN7523_CLK_SLIC, + .name = "slic", + + .base_reg = REG_SPI_CLK_FREQ_SEL, + .base_bits = 1, + .base_shift = 0, + .base_values = slic_base, + .n_base_values = ARRAY_SIZE(slic_base), + + .div_reg = REG_SPI_CLK_DIV_SEL, + .div_bits = 5, + .div_shift = 24, + .div_val0 = 20, + .div_step = 2, + }, { + .id = EN7523_CLK_SPI, + .name = "spi", + + .base_reg = REG_SPI_CLK_DIV_SEL, + + .base_value = 400000000, + + .div_bits = 5, + .div_shift = 8, + .div_val0 = 40, + .div_step = 2, + }, { + .id = EN7523_CLK_NPU, + .name = "npu", + + .base_reg = REG_NPU_CLK_DIV_SEL, + .base_bits = 2, + .base_shift = 8, + .base_values = npu_base, + .n_base_values = ARRAY_SIZE(npu_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + }, { + .id = EN7523_CLK_CRYPTO, + .name = "crypto", + + .base_reg = REG_CRYPTO_CLKSRC, + .base_bits = 1, + .base_shift = 8, + .base_values = emi_base, + .n_base_values = ARRAY_SIZE(emi_base), + } +}; + +static const struct of_device_id of_match_clk_en7523[] = { + { .compatible = "airoha,en7523-scu", }, + { /* sentinel */ } +}; + +static u32 en7523_get_base_rate(void __iomem *base, int i) +{ + const struct en_clk_desc *desc = &en7523_base_clks[i]; + u32 val; + + if (!desc->base_bits) + return desc->base_value; + + val = readl(base + desc->base_reg); + val >>= desc->base_shift; + val &= (1 << desc->base_bits) - 1; + + if (val >= desc->n_base_values) + return 0; + + return desc->base_values[val]; +} + +static u32 en7523_get_div(void __iomem *base, int i) +{ + const struct en_clk_desc *desc = &en7523_base_clks[i]; + u32 reg, val; + + if (!desc->div_bits) + return 1; + + reg = desc->div_reg ? desc->div_reg : desc->base_reg; + val = readl(base + reg); + val >>= desc->div_shift; + val &= (1 << desc->div_bits) - 1; + + if (!val && desc->div_val0) + return desc->div_val0; + + return (val + 1) * desc->div_step; +} + +static int en7523_pci_is_enabled(struct clk_hw *hw) +{ + struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); + + return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1); +} + +static int en7523_pci_enable(struct clk_hw *hw) +{ + struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); + void *np_base = cg->base; + u32 val, mask; + + /* Need to pull device low before reset */ + val = readl(np_base + REG_PCI_CONTROL); + val &= ~(REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT); + writel(val, np_base + REG_PCI_CONTROL); + usleep_range(1000, 2000); + + /* Enable PCIe port 1 */ + val |= REG_PCI_CONTROL_REFCLK_EN1; + writel(val, np_base + REG_PCI_CONTROL); + usleep_range(1000, 2000); + + /* Reset to default */ + val = readl(np_base + REG_RESET_CONTROL); + mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 | + REG_RESET_CONTROL_PCIEHB; + writel(val & ~mask, np_base + REG_RESET_CONTROL); + usleep_range(1000, 2000); + writel(val | mask, np_base + REG_RESET_CONTROL); + msleep(100); + writel(val & ~mask, np_base + REG_RESET_CONTROL); + usleep_range(5000, 10000); + + /* Release device */ + mask = REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT; + val = readl(np_base + REG_PCI_CONTROL); + writel(val & ~mask, np_base + REG_PCI_CONTROL); + usleep_range(1000, 2000); + writel(val | mask, np_base + REG_PCI_CONTROL); + msleep(250); + + return 0; +} + +static void en7523_pci_disable(struct clk_hw *hw) +{ + struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); + void *np_base = cg->base; + u32 val; + + val = readl(np_base + REG_PCI_CONTROL); + val &= ~REG_PCI_CONTROL_REFCLK_EN1; + writel(val, np_base + REG_PCI_CONTROL); +} + +static struct clk *en7523_register_pcie_clk(struct device *dev, + void __iomem *np_base) +{ + static const struct clk_ops pcie_gate_ops = { + .is_enabled = en7523_pci_is_enabled, + .enable = en7523_pci_enable, + .disable = en7523_pci_disable, + }; + struct clk_init_data init = { + .name = "pcie", + .ops = &pcie_gate_ops, + }; + struct en_clk_gate *cg; + struct clk *clk; + + cg = devm_kzalloc(dev, sizeof(*cg), GFP_KERNEL); + if (!cg) + return NULL; + + cg->base = np_base; + cg->hw.init = &init; + en7523_pci_disable(&cg->hw); + + clk = clk_register(NULL, &cg->hw); + if (IS_ERR(clk)) + clk = NULL; + + return clk; +} + +static void en7523_register_clocks(struct device *dev, struct clk_onecell_data *clk_data, + void __iomem *base, void __iomem *np_base) +{ + struct clk *clk; + u32 rate; + int i; + + for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) { + const struct en_clk_desc *desc = &en7523_base_clks[i]; + + rate = en7523_get_base_rate(base, i); + rate /= en7523_get_div(base, i); + + clk = clk_register_fixed_rate(NULL, desc->name, NULL, 0, rate); + if (IS_ERR(clk)) { + pr_err("Failed to register clk %s: %ld\n", + desc->name, PTR_ERR(clk)); + continue; + } + + clk_data->clks[desc->id] = clk; + } + + clk = en7523_register_pcie_clk(dev, np_base); + clk_data->clks[EN7523_CLK_PCIE] = clk; + + clk_data->clk_num = EN7523_NUM_CLOCKS; +} + +static int en7523_clk_probe(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct clk_onecell_data *clk_data; + void __iomem *base, *np_base; + int r; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + np_base = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(base)) + return PTR_ERR(np_base); + + clk_data = devm_kzalloc(&pdev->dev, sizeof(*clk_data), GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + clk_data->clks = devm_kcalloc(&pdev->dev, EN7523_NUM_CLOCKS, + sizeof(*clk_data->clks), GFP_KERNEL); + if (!clk_data->clks) + return -ENOMEM; + + en7523_register_clocks(&pdev->dev, clk_data, base, np_base); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) + dev_err(&pdev->dev, + "could not register clock provider: %s: %d\n", + pdev->name, r); + + return r; +} + +static struct platform_driver clk_en7523_drv = { + .probe = en7523_clk_probe, + .driver = { + .name = "clk-en7523", + .of_match_table = of_match_clk_en7523, + }, +}; + +static int clk_en7523_init(void) +{ + return platform_driver_register(&clk_en7523_drv); +} + +arch_initcall(clk_en7523_init);
This driver only registers fixed rate clocks, since the clocks are fully initialized by the boot loader and should not be changed later, according to Airoha. Signed-off-by: Felix Fietkau <nbd@nbd.name> --- arch/arm/boot/dts/en7523.dtsi | 8 + drivers/clk/Kconfig | 9 + drivers/clk/Makefile | 1 + drivers/clk/clk-en7523.c | 356 ++++++++++++++++++++++++++++++++++ 4 files changed, 374 insertions(+) create mode 100644 drivers/clk/clk-en7523.c