| Message ID | 20211220211854.89452-4-nbd@nbd.name (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add support for Airoha EN7523 SoC | expand |
On 2021-12-20 21:18, Felix Fietkau wrote: > From: John Crispin <john@phrozen.org> > > Add basic support for Airoha EN7523, enough for booting to console. > > The UART is basically 8250-compatible, except for the clock selection. > A clock-frequency value is synthesized to get this to run at 115200 > bps. > > Signed-off-by: John Crispin <john@phrozen.org> > Signed-off-by: Bert Vermeulen <bert@biot.com> > Signed-off-by: Felix Fietkau <nbd@nbd.name> > --- > arch/arm/boot/dts/Makefile | 2 + > arch/arm/boot/dts/en7523-evb.dts | 27 ++++++++ > arch/arm/boot/dts/en7523.dtsi | 114 +++++++++++++++++++++++++++++++ > 3 files changed, 143 insertions(+) > create mode 100644 arch/arm/boot/dts/en7523-evb.dts > create mode 100644 arch/arm/boot/dts/en7523.dtsi > [...] > + gic: interrupt-controller@9000000 { > + compatible = "arm,gic-v3"; > + interrupt-controller; > + #interrupt-cells = <3>; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x09000000 0x20000>, <0x09080000 0x80000>; You are missing the 3 extra regions implemented by the A53 cores (GICC, GICV, GICH). Please see the binding and the A53 TRM. > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; > + }; > + > + timer { > + compatible = "arm,armv7-timer"; This is an ARMv8 CPU, even when used in 32bit mode. > + interrupt-parent = <&gic>; > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, > + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, > + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, > + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; > + clock-frequency = <25000000>; Why isn't this properly configured by the firmware? M.
On 2021-12-21 16:02, Marc Zyngier wrote: > On 2021-12-20 21:18, Felix Fietkau wrote: >> From: John Crispin <john@phrozen.org> >> >> Add basic support for Airoha EN7523, enough for booting to console. >> >> The UART is basically 8250-compatible, except for the clock selection. >> A clock-frequency value is synthesized to get this to run at 115200 >> bps. >> >> Signed-off-by: John Crispin <john@phrozen.org> >> Signed-off-by: Bert Vermeulen <bert@biot.com> >> Signed-off-by: Felix Fietkau <nbd@nbd.name> >> --- >> arch/arm/boot/dts/Makefile | 2 + >> arch/arm/boot/dts/en7523-evb.dts | 27 ++++++++ >> arch/arm/boot/dts/en7523.dtsi | 114 +++++++++++++++++++++++++++++++ >> 3 files changed, 143 insertions(+) >> create mode 100644 arch/arm/boot/dts/en7523-evb.dts >> create mode 100644 arch/arm/boot/dts/en7523.dtsi >> > > [...] > >> + gic: interrupt-controller@9000000 { >> + compatible = "arm,gic-v3"; >> + interrupt-controller; >> + #interrupt-cells = <3>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + reg = <0x09000000 0x20000>, <0x09080000 0x80000>; > > You are missing the 3 extra regions implemented by the A53 cores > (GICC, GICV, GICH). Please see the binding and the A53 TRM. The SoC memory map documentation contains an address for GICC, but not for the other two. Maybe this CPU doesn't implement them. I will add GICC in v9 >> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; >> + }; >> + >> + timer { >> + compatible = "arm,armv7-timer"; > > This is an ARMv8 CPU, even when used in 32bit mode. > >> + interrupt-parent = <&gic>; >> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, >> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, >> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, >> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; >> + clock-frequency = <25000000>; > > Why isn't this properly configured by the firmware? I don't know. - Felix
On Wed, 22 Dec 2021 16:04:07 +0000, Felix Fietkau <nbd@nbd.name> wrote: > > > On 2021-12-21 16:02, Marc Zyngier wrote: > > On 2021-12-20 21:18, Felix Fietkau wrote: > >> From: John Crispin <john@phrozen.org> > >> > >> Add basic support for Airoha EN7523, enough for booting to console. > >> > >> The UART is basically 8250-compatible, except for the clock selection. > >> A clock-frequency value is synthesized to get this to run at 115200 > >> bps. > >> > >> Signed-off-by: John Crispin <john@phrozen.org> > >> Signed-off-by: Bert Vermeulen <bert@biot.com> > >> Signed-off-by: Felix Fietkau <nbd@nbd.name> > >> --- > >> arch/arm/boot/dts/Makefile | 2 + > >> arch/arm/boot/dts/en7523-evb.dts | 27 ++++++++ > >> arch/arm/boot/dts/en7523.dtsi | 114 +++++++++++++++++++++++++++++++ > >> 3 files changed, 143 insertions(+) > >> create mode 100644 arch/arm/boot/dts/en7523-evb.dts > >> create mode 100644 arch/arm/boot/dts/en7523.dtsi > >> > > > > [...] > > > >> + gic: interrupt-controller@9000000 { > >> + compatible = "arm,gic-v3"; > >> + interrupt-controller; > >> + #interrupt-cells = <3>; > >> + #address-cells = <1>; > >> + #size-cells = <1>; > >> + reg = <0x09000000 0x20000>, <0x09080000 0x80000>; > > > > You are missing the 3 extra regions implemented by the A53 cores > > (GICC, GICV, GICH). Please see the binding and the A53 TRM. > The SoC memory map documentation contains an address for GICC, but not > for the other two. Maybe this CPU doesn't implement them. Please read the CPU TRM (it is publicly available from the ARM web site). GICC, GICV and GICH are all at a fixed offset form each other, and are always implemented by the A53 when connected to a GICv3. > I will add GICC in v9 Please add all 3 missing regions. > > >> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; > >> + }; > >> + > >> + timer { > >> + compatible = "arm,armv7-timer"; > > > > This is an ARMv8 CPU, even when used in 32bit mode. > > > >> + interrupt-parent = <&gic>; > >> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, > >> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, > >> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, > >> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; > >> + clock-frequency = <25000000>; > > > > Why isn't this properly configured by the firmware? > I don't know. Then drop it. Thanks, M.
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0de64f237cd8..81cb49f8d6fd 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -186,6 +186,8 @@ dtb-$(CONFIG_ARCH_DAVINCI) += \ da850-lego-ev3.dtb dtb-$(CONFIG_ARCH_DIGICOLOR) += \ cx92755_equinox.dtb +dtb-$(CONFIG_ARCH_AIROHA) += \ + en7523-evb.dtb dtb-$(CONFIG_ARCH_EXYNOS3) += \ exynos3250-artik5-eval.dtb \ exynos3250-monk.dtb \ diff --git a/arch/arm/boot/dts/en7523-evb.dts b/arch/arm/boot/dts/en7523-evb.dts new file mode 100644 index 000000000000..69754ef9a628 --- /dev/null +++ b/arch/arm/boot/dts/en7523-evb.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/dts-v1/; + +/* Bootloader installs ATF here */ +/memreserve/ 0x80000000 0x200000; + +#include "en7523.dtsi" + +/ { + model = "Airoha EN7523 Evaluation Board"; + compatible = "airoha,en7523-evb", "airoha,en7523"; + + aliases { + serial0 = &uart1; + }; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + stdout-path = "serial0:115200n8"; + linux,usable-memory-range = <0x80200000 0x1fe00000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; +}; diff --git a/arch/arm/boot/dts/en7523.dtsi b/arch/arm/boot/dts/en7523.dtsi new file mode 100644 index 000000000000..7e17311a3f90 --- /dev/null +++ b/arch/arm/boot/dts/en7523.dtsi @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + npu_binary@84000000 { + no-map; + reg = <0x84000000 0xA00000>; + }; + + npu_flag@84B0000 { + no-map; + reg = <0x84B00000 0x100000>; + }; + + npu_pkt@85000000 { + no-map; + reg = <0x85000000 0x1A00000>; + }; + + npu_phyaddr@86B00000 { + no-map; + reg = <0x86B00000 0x100000>; + }; + + npu_rxdesc@86D00000 { + no-map; + reg = <0x86D00000 0x100000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + clock-frequency = <80000000>; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + clock-frequency = <80000000>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + gic: interrupt-controller@9000000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x09000000 0x20000>, <0x09080000 0x80000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + clock-frequency = <25000000>; + }; + + uart1: serial@1fbf0000 { + compatible = "ns16550"; + reg = <0x1fbf0000 0x30>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <1843200>; + status = "okay"; + }; +};