diff mbox series

ARM: dts: bcm2837: Add the missing L1/L2 cache information

Message ID 20211218200009.16856-1-rs@noreya.tech (mailing list archive)
State New, archived
Headers show
Series ARM: dts: bcm2837: Add the missing L1/L2 cache information | expand

Commit Message

Richard Schleich Dec. 18, 2021, 8 p.m. UTC 
This patch fixes the kernel warning
"cacheinfo: Unable to detect cache hierarchy for CPU 0"
for the bcm2837 on newer kernel versions.

Signed-off-by: Richard Schleich <rs@noreya.tech>
---
 arch/arm/boot/dts/bcm2837.dtsi | 49 ++++++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

Comments

Stefan Wahren Dec. 28, 2021, 5:52 p.m. UTC | #1 
Am 18.12.21 um 21:00 schrieb Richard Schleich:
> This patch fixes the kernel warning
> "cacheinfo: Unable to detect cache hierarchy for CPU 0"
> for the bcm2837 on newer kernel versions.
>
> Signed-off-by: Richard Schleich <rs@noreya.tech>

Tested-by: Stefan Wahren <stefan.wahren@i2se.com>

I tested the patch with a Raspberry Pi 3 B Plus (arm64/defconfig) and here are
some outputs:

/sys/devices/system/cpu/cpu0/cache

./index2/number_of_sets:512
./index2/ways_of_associativity:16
./index2/shared_cpu_list:0-3
./index2/type:Unified
./index2/size:512K
./index2/level:2
./index2/coherency_line_size:64
./index2/shared_cpu_map:f
./index0/number_of_sets:128
./index0/ways_of_associativity:4
./index0/shared_cpu_list:0
./index0/type:Data
./index0/size:32K
./index0/level:1
./index0/coherency_line_size:64
./index0/shared_cpu_map:1
./index1/number_of_sets:256
./index1/ways_of_associativity:2
./index1/shared_cpu_list:0
./index1/type:Instruction
./index1/size:32K
./index1/level:1
./index1/coherency_line_size:64
./index1/shared_cpu_map:1

lscpu

Architecture:        aarch64
Byte Order:          Little Endian
CPU(s):              4
On-line CPU(s) list: 0-3
Thread(s) per core:  1
Core(s) per socket:  4
Socket(s):           1
NUMA node(s):        1
Vendor ID:           ARM
Model:               4
Model name:          Cortex-A53
Stepping:            r0p4
CPU max MHz:         1400,0000
CPU min MHz:         600,0000
BogoMIPS:            38.40
L1d cache:           32K
L1i cache:           32K
L2 cache:            512K
NUMA node0 CPU(s):   0-3
Flags:               fp asimd evtstrm crc32 cpuid
Florian Fainelli Feb. 1, 2022, 12:24 a.m. UTC | #2 
On Sat, 18 Dec 2021 21:00:09 +0100, Richard Schleich <rs@noreya.tech> wrote:
> This patch fixes the kernel warning
> "cacheinfo: Unable to detect cache hierarchy for CPU 0"
> for the bcm2837 on newer kernel versions.
> 
> Signed-off-by: Richard Schleich <rs@noreya.tech>
> ---

Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks!
--
Florian
Florian Fainelli Feb. 1, 2022, 12:29 a.m. UTC | #3 
On 1/31/2022 4:24 PM, Florian Fainelli wrote:
> On Sat, 18 Dec 2021 21:00:09 +0100, Richard Schleich <rs@noreya.tech> wrote:
>> This patch fixes the kernel warning
>> "cacheinfo: Unable to detect cache hierarchy for CPU 0"
>> for the bcm2837 on newer kernel versions.
>>
>> Signed-off-by: Richard Schleich <rs@noreya.tech>
>> ---
> 
> Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks!

I did remove the comments that were not helpful for the 'd-cache-size', 
'd-cache-line-size', 'i-cache-size' and 'i-cache-line-size'  since they 
are self explanatory.

Thanks!
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi
index 0199ec98cd61..1af1616982bb 100644
--- a/arch/arm/boot/dts/bcm2837.dtsi
+++ b/arch/arm/boot/dts/bcm2837.dtsi
@@ -40,12 +40,26 @@ 
 		#size-cells = <0>;
 		enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
 
+		/* Source for d/i-cache-line-size and d/i-cache-sets
+		 *  https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system
+		 *  /about-the-l1-memory-system?lang=en
+		 *
+		 *  Source for d/i-cache-size
+		 *  https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks
+		 */
 		cpu0: cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53";
 			reg = <0>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0x0 0x000000d8>;
+			d-cache-size = <0x8000>; // 32KiB
+			d-cache-line-size = <64>;// Data side cache line length of 64 bytes
+			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
+			i-cache-size = <0x8000>; // 32KiB
+			i-cache-line-size = <64>;// Instruction side cache line length of 64 bytes
+			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+			next-level-cache = <&l2>;
 		};
 
 		cpu1: cpu@1 {
@@ -54,6 +68,13 @@ 
 			reg = <1>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0x0 0x000000e0>;
+			d-cache-size = <0x8000>; // 32KiB
+			d-cache-line-size = <64>;// Data side cache line length of 64 bytes
+			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
+			i-cache-size = <0x8000>; // 32KiB
+			i-cache-line-size = <64>;// Instruction side cache line length of 64 bytes
+			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+			next-level-cache = <&l2>;
 		};
 
 		cpu2: cpu@2 {
@@ -62,6 +83,13 @@ 
 			reg = <2>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0x0 0x000000e8>;
+			d-cache-size = <0x8000>; // 32KiB
+			d-cache-line-size = <64>;// Data side cache line length of 64 bytes
+			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
+			i-cache-size = <0x8000>; // 32KiB
+			i-cache-line-size = <64>;// Instruction side cache line length of 64 bytes
+			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+			next-level-cache = <&l2>;
 		};
 
 		cpu3: cpu@3 {
@@ -70,6 +98,27 @@ 
 			reg = <3>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0x0 0x000000f0>;
+			d-cache-size = <0x8000>; // 32KiB
+			d-cache-line-size = <64>;// Data side cache line length of 64 bytes
+			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
+			i-cache-size = <0x8000>; // 32KiB
+			i-cache-line-size = <64>;// Instruction side cache line length of 64 bytes
+			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+			next-level-cache = <&l2>;
+		};
+
+		l2: l2-cache0 {
+		 /*  Source for cache-line-size + cache-sets
+		  *  https://developer.arm.com/documentation/ddi0500
+		  *  /e/level-2-memory-system/about-the-l2-memory-system?lang=en
+		  *  Source for cache-size
+		  *  https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf
+		  */
+			compatible = "cache";
+			cache-size = <0x80000>; // 512KiB
+			cache-line-size = <64>; // Fixed line length of 64 bytes
+			cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set
+			cache-level = <2>;
 		};
 	};
 };