| Message ID | 20220103143712.46675-2-angelogioacchino.delregno@collabora.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] clk: mediatek: clk-gate: Shrink by adding clockgating bit check helper | expand |
On Mon, Jan 3, 2022 at 10:38 PM AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> wrote: > > Appropriately change calls to regmap_update_bits() with regmap_set_bits() > and regmap_clear_bits() for improved readability. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Quoting AngeloGioacchino Del Regno (2022-01-03 06:37:12) > Appropriately change calls to regmap_update_bits() with regmap_set_bits() > and regmap_clear_bits() for improved readability. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- Applied to clk-next
diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c index 957fa1d68f07..5d88b428565b 100644 --- a/drivers/clk/mediatek/clk-gate.c +++ b/drivers/clk/mediatek/clk-gate.c @@ -53,17 +53,15 @@ static void mtk_cg_clr_bit(struct clk_hw *hw) static void mtk_cg_set_bit_no_setclr(struct clk_hw *hw) { struct mtk_clk_gate *cg = to_mtk_clk_gate(hw); - u32 cgbit = BIT(cg->bit); - regmap_update_bits(cg->regmap, cg->sta_ofs, cgbit, cgbit); + regmap_set_bits(cg->regmap, cg->sta_ofs, BIT(cg->bit)); } static void mtk_cg_clr_bit_no_setclr(struct clk_hw *hw) { struct mtk_clk_gate *cg = to_mtk_clk_gate(hw); - u32 cgbit = BIT(cg->bit); - regmap_update_bits(cg->regmap, cg->sta_ofs, cgbit, 0); + regmap_clear_bits(cg->regmap, cg->sta_ofs, BIT(cg->bit)); } static int mtk_cg_enable(struct clk_hw *hw)
Appropriately change calls to regmap_update_bits() with regmap_set_bits() and regmap_clear_bits() for improved readability. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- drivers/clk/mediatek/clk-gate.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)