Message ID | 20220106032420.11544-2-allen-kh.cheng@mediatek.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Update MT8192 Clock Setting | expand |
Hi Allen, thank you for improving the commit message! However, please see my comment below. On Thu, Jan 06, 2022 at 11:24:16AM +0800, allen-kh.cheng wrote: > From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com> > > When the initial devicetree for mt8192 was added in 48489980e27e ("arm64: > dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile"), the > clock driver for mt8192 was not yet upstream, so the clock property nodes > were set to the clk26m clock as a placeholder. > > Given that the clock driver has since been added through 710573dee31b ("clk: > mediatek: Add MT8192 basic clocks support"), as well as its dt-bindings > through f35f1a23e0e1 ("clk: mediatek: Add dt-bindings of MT8192 clocks") and > devicetree nodes through 5d2b897bc6f5 ("arm64: dts: mediatek: Add mt8192 > clock controllers"), fix the uart clock property to point to the actual This sentence is incomplete. It is missing "clock." at the end. Could you please add it? Same thing for all other patches in this series. After fixing that typo in the commit message of all patches, please add my reviewed-by in all patches: Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Thanks, Nícolas
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index c7c7d4e017ae..cfb67cc40c2c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -327,7 +327,7 @@ "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x1000>; interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&clk26m>, <&clk26m>; + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; clock-names = "baud", "bus"; status = "disabled"; }; @@ -337,7 +337,7 @@ "mediatek,mt6577-uart"; reg = <0 0x11003000 0 0x1000>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&clk26m>, <&clk26m>; + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; clock-names = "baud", "bus"; status = "disabled"; };