diff mbox series

[3/5] drm/stm: ltdc: add per plane update support

Message ID 20211215214817.20310-1-yannick.fertre@foss.st.com (mailing list archive)
State New, archived
Headers show
Series drm/stm: new features to display controller | expand

Commit Message

Yannick Fertre Dec. 15, 2021, 9:48 p.m. UTC 
Recent ltdc hardware versions offer the ability
to update a plane independently of others planes.
This is could be useful especially if a plane is
assigned to another OS.

Signed-off-by: Yannick Fertre <yannick.fertre@foss.st.com>
---
 drivers/gpu/drm/stm/ltdc.c | 26 +++++++++++++++++++++++---
 drivers/gpu/drm/stm/ltdc.h |  1 +
 2 files changed, 24 insertions(+), 3 deletions(-)

Comments

Philippe CORNU Jan. 4, 2022, 10:24 a.m. UTC | #1 
On 12/15/21 10:48 PM, Yannick Fertre wrote:
> Recent ltdc hardware versions offer the ability
> to update a plane independently of others planes.
> This is could be useful especially if a plane is
> assigned to another OS.
> 
> Signed-off-by: Yannick Fertre <yannick.fertre@foss.st.com>
> ---
>   drivers/gpu/drm/stm/ltdc.c | 26 +++++++++++++++++++++++---
>   drivers/gpu/drm/stm/ltdc.h |  1 +
>   2 files changed, 24 insertions(+), 3 deletions(-)
> 

Hi Yannick,
many thanks for your patch.
Acked-by: Philippe Cornu <philippe.cornu@foss.st.com>
Reviewed-by: Philippe Cornu <philippe.cornu@foss.st.com>
Philippe :-)
Raphael Gallais-Pou Jan. 13, 2022, 9:59 a.m. UTC | #2 
On 12/15/21 10:48 PM, Yannick Fertre wrote:
> Recent ltdc hardware versions offer the ability
> to update a plane independently of others planes.
> This is could be useful especially if a plane is
> assigned to another OS.
>
> Signed-off-by: Yannick Fertre <yannick.fertre@foss.st.com>
> ---
>  drivers/gpu/drm/stm/ltdc.c | 26 +++++++++++++++++++++++---
>  drivers/gpu/drm/stm/ltdc.h |  1 +
>  2 files changed, 24 insertions(+), 3 deletions(-)

Hello Yannick,

Reviewed-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>

Thank you for this patch,
Raphaël
diff mbox series

Patch

diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
index b819f4cbcc3d..862d43fe3087 100644
--- a/drivers/gpu/drm/stm/ltdc.c
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -197,6 +197,10 @@ 
 
 #define LXCFBLNR_CFBLN	GENMASK(10, 0)	/* Color Frame Buffer Line Number */
 
+#define LXRCR_IMR	BIT(0)		/* IMmediate Reload */
+#define LXRCR_VBR	BIT(1)		/* Vertical Blanking Reload */
+#define LXRCR_GRMSK	BIT(2)		/* Global (centralized) Reload MaSKed */
+
 #define CLUT_SIZE	256
 
 #define CONSTA_MAX	0xFF		/* CONSTant Alpha MAX= 1.0 */
@@ -534,7 +538,8 @@  static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc,
 	regmap_set_bits(ldev->regmap, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
 
 	/* Commit shadow registers = update planes at next vblank */
-	regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR);
+	if (!ldev->caps.plane_reg_shadow)
+		regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR);
 
 	drm_crtc_vblank_on(crtc);
 }
@@ -553,7 +558,8 @@  static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc,
 	regmap_clear_bits(ldev->regmap, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
 
 	/* immediately commit disable of layers before switching off LTDC */
-	regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_IMR);
+	if (!ldev->caps.plane_reg_shadow)
+		regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_IMR);
 
 	pm_runtime_put_sync(ddev->dev);
 }
@@ -769,7 +775,8 @@  static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc,
 	ltdc_crtc_update_clut(crtc);
 
 	/* Commit shadow registers = update planes at next vblank */
-	regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR);
+	if (!ldev->caps.plane_reg_shadow)
+		regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR);
 
 	if (event) {
 		crtc->state->event = NULL;
@@ -1010,6 +1017,11 @@  static void ltdc_plane_atomic_update(struct drm_plane *plane,
 	val |= LXCR_LEN;
 	regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_LEN | LXCR_CLUTEN, val);
 
+	/* Commit shadow registers = update plane at next vblank */
+	if (ldev->caps.plane_reg_shadow)
+		regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs,
+				  LXRCR_IMR | LXRCR_VBR | LXRCR_GRMSK, LXRCR_VBR);
+
 	ldev->plane_fpsi[plane->index].counter++;
 
 	mutex_lock(&ldev->err_lock);
@@ -1035,6 +1047,11 @@  static void ltdc_plane_atomic_disable(struct drm_plane *plane,
 	/* disable layer */
 	regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_LEN, 0);
 
+	/* Commit shadow registers = update plane at next vblank */
+	if (ldev->caps.plane_reg_shadow)
+		regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs,
+				  LXRCR_IMR | LXRCR_VBR | LXRCR_GRMSK, LXRCR_VBR);
+
 	DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n",
 			 oldstate->crtc->base.id, plane->base.id);
 }
@@ -1307,6 +1324,7 @@  static int ltdc_get_caps(struct drm_device *ddev)
 			ldev->caps.pad_max_freq_hz = 65000000;
 		ldev->caps.nb_irq = 2;
 		ldev->caps.ycbcr_output = false;
+		ldev->caps.plane_reg_shadow = false;
 		break;
 	case HWVER_20101:
 		ldev->caps.layer_ofs = LAY_OFS_0;
@@ -1316,6 +1334,7 @@  static int ltdc_get_caps(struct drm_device *ddev)
 		ldev->caps.pad_max_freq_hz = 150000000;
 		ldev->caps.nb_irq = 4;
 		ldev->caps.ycbcr_output = false;
+		ldev->caps.plane_reg_shadow = false;
 		break;
 	case HWVER_40100:
 		ldev->caps.layer_ofs = LAY_OFS_1;
@@ -1325,6 +1344,7 @@  static int ltdc_get_caps(struct drm_device *ddev)
 		ldev->caps.pad_max_freq_hz = 90000000;
 		ldev->caps.nb_irq = 2;
 		ldev->caps.ycbcr_output = true;
+		ldev->caps.plane_reg_shadow = true;
 		break;
 	default:
 		return -ENODEV;
diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h
index f04fcebb5223..68a5a199e320 100644
--- a/drivers/gpu/drm/stm/ltdc.h
+++ b/drivers/gpu/drm/stm/ltdc.h
@@ -22,6 +22,7 @@  struct ltdc_caps {
 	int pad_max_freq_hz;	/* max frequency supported by pad */
 	int nb_irq;		/* number of hardware interrupts */
 	bool ycbcr_output;	/* ycbcr output converter supported */
+	bool plane_reg_shadow;	/* plane shadow registers ability */
 };
 
 #define LTDC_MAX_LAYER	4