| Message ID | 20220121193544.23231-4-romain.perier@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ARM: mstar: cpupll | expand |
Hi Romain, On Sat, 22 Jan 2022 at 04:35, Romain Perier <romain.perier@gmail.com> wrote: > > From: Daniel Palmer <daniel@0x0f.com> > > All MStar/SigmaStar ARMv7 SoCs have the CPU PLL at the same > place so add it to the base dtsi. > > Signed-off-by: Daniel Palmer <daniel@0x0f.com> > --- > arch/arm/boot/dts/mstar-v7.dtsi | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi > index 89ebfe4f29da..2249faaa3aa7 100644 > --- a/arch/arm/boot/dts/mstar-v7.dtsi > +++ b/arch/arm/boot/dts/mstar-v7.dtsi > @@ -155,6 +155,13 @@ mpll: mpll@206000 { > clocks = <&xtal>; > }; > > + cpupll: cpupll@206400 { > + compatible = "mstar,msc313-cpupll"; > + reg = <0x206400 0x200>; > + #clock-cells = <0>; > + clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>; > + }; > + > gpio: gpio@207800 { > #gpio-cells = <2>; > reg = <0x207800 0x200>; > -- > 2.34.1 > I guess I can't add a reviewed by for my own commit but this looks good to me. The same CPUPLL is present on all of the chips seen so far so this is the right place for this. Cheers, Daniel
diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 89ebfe4f29da..2249faaa3aa7 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -155,6 +155,13 @@ mpll: mpll@206000 { clocks = <&xtal>; }; + cpupll: cpupll@206400 { + compatible = "mstar,msc313-cpupll"; + reg = <0x206400 0x200>; + #clock-cells = <0>; + clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>; + }; + gpio: gpio@207800 { #gpio-cells = <2>; reg = <0x207800 0x200>;