| Message ID | 20220124184605.999353-5-farosas@linux.ibm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/ppc: powerpc_excp improvements [BookS] (4/n) | expand |
On 1/24/22 19:46, Fabiano Rosas wrote: > Since this is now BookS only, we can simplify the code a bit and check > has_hv_mode instead of enumerating the exception models. LPES0 does > not make sense if there is no MSR_HV. > > Note that QEMU does not support HV mode on 970 and POWER5+ so we don't > set MSR_HV in msr_mask. HV mode is not supported on POWER7 also. > Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Anyhow, Reviewed-by: Cédric Le Goater <clg@kaod.org> Thanks, C. > --- > target/ppc/excp_helper.c | 30 +++++++----------------------- > 1 file changed, 7 insertions(+), 23 deletions(-) > > diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c > index e5f09e1984..67faec3775 100644 > --- a/target/ppc/excp_helper.c > +++ b/target/ppc/excp_helper.c > @@ -644,39 +644,23 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp) > { > bool lpes0; > > - cs = CPU(cpu); > - > /* > - * Exception targeting modifiers > - * > - * LPES0 is supported on POWER7/8/9 > - * LPES1 is not supported (old iSeries mode) > - * > - * On anything else, we behave as if LPES0 is 1 > - * (externals don't alter MSR:HV) > + * LPES0 is only taken into consideration if we support HV > + * mode for this CPU. > */ > -#if defined(TARGET_PPC64) > - if (excp_model == POWERPC_EXCP_POWER7 || > - excp_model == POWERPC_EXCP_POWER8 || > - excp_model == POWERPC_EXCP_POWER9 || > - excp_model == POWERPC_EXCP_POWER10) { > - lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); > - } else > -#endif /* defined(TARGET_PPC64) */ > - { > - lpes0 = true; > + if (!env->has_hv_mode) { > + break; > } > > + lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); > + > if (!lpes0) { > new_msr |= (target_ulong)MSR_HVB; > new_msr |= env->msr & ((target_ulong)1 << MSR_RI); > srr0 = SPR_HSRR0; > srr1 = SPR_HSRR1; > } > - if (env->mpic_proxy) { > - /* IACK the IRQ on delivery */ > - env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack); > - } > + > break; > } > case POWERPC_EXCP_ALIGN: /* Alignment exception */ >
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index e5f09e1984..67faec3775 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -644,39 +644,23 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp) { bool lpes0; - cs = CPU(cpu); - /* - * Exception targeting modifiers - * - * LPES0 is supported on POWER7/8/9 - * LPES1 is not supported (old iSeries mode) - * - * On anything else, we behave as if LPES0 is 1 - * (externals don't alter MSR:HV) + * LPES0 is only taken into consideration if we support HV + * mode for this CPU. */ -#if defined(TARGET_PPC64) - if (excp_model == POWERPC_EXCP_POWER7 || - excp_model == POWERPC_EXCP_POWER8 || - excp_model == POWERPC_EXCP_POWER9 || - excp_model == POWERPC_EXCP_POWER10) { - lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); - } else -#endif /* defined(TARGET_PPC64) */ - { - lpes0 = true; + if (!env->has_hv_mode) { + break; } + lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); + if (!lpes0) { new_msr |= (target_ulong)MSR_HVB; new_msr |= env->msr & ((target_ulong)1 << MSR_RI); srr0 = SPR_HSRR0; srr1 = SPR_HSRR1; } - if (env->mpic_proxy) { - /* IACK the IRQ on delivery */ - env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack); - } + break; } case POWERPC_EXCP_ALIGN: /* Alignment exception */
Since this is now BookS only, we can simplify the code a bit and check has_hv_mode instead of enumerating the exception models. LPES0 does not make sense if there is no MSR_HV. Note that QEMU does not support HV mode on 970 and POWER5+ so we don't set MSR_HV in msr_mask. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> --- target/ppc/excp_helper.c | 30 +++++++----------------------- 1 file changed, 7 insertions(+), 23 deletions(-)