| Message ID | 8717d91000002047c7d0925f5eae66fc7f795e27.1643077283.git.ming.qian@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | amphion video decoder/encoder driver | expand |
Shawn, can you Ack this? I think it makes sense if I take this one through the media subsystem. Alternatively, if you prefer to take this patch yourself, then let me know. Regards, Hans On 25/01/2022 08:11, Ming Qian wrote: > the vpu core depends on the mu resources. > if they're missed, the vpu can't work. > > Signed-off-by: Ming Qian <ming.qian@nxp.com> > Signed-off-by: Shijie Qin <shijie.qin@nxp.com> > Signed-off-by: Zhou Peng <eagle.zhou@nxp.com> > --- > drivers/firmware/imx/scu-pd.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/firmware/imx/scu-pd.c b/drivers/firmware/imx/scu-pd.c > index ff6569c4a53b..af3d057e6421 100644 > --- a/drivers/firmware/imx/scu-pd.c > +++ b/drivers/firmware/imx/scu-pd.c > @@ -155,6 +155,10 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { > { "vpu-pid", IMX_SC_R_VPU_PID0, 8, true, 0 }, > { "vpu-dec0", IMX_SC_R_VPU_DEC_0, 1, false, 0 }, > { "vpu-enc0", IMX_SC_R_VPU_ENC_0, 1, false, 0 }, > + { "vpu-enc1", IMX_SC_R_VPU_ENC_1, 1, false, 0 }, > + { "vpu-mu0", IMX_SC_R_VPU_MU_0, 1, false, 0 }, > + { "vpu-mu1", IMX_SC_R_VPU_MU_1, 1, false, 0 }, > + { "vpu-mu2", IMX_SC_R_VPU_MU_2, 1, false, 0 }, > > /* GPU SS */ > { "gpu0-pid", IMX_SC_R_GPU_0_PID0, 4, true, 0 },
diff --git a/drivers/firmware/imx/scu-pd.c b/drivers/firmware/imx/scu-pd.c index ff6569c4a53b..af3d057e6421 100644 --- a/drivers/firmware/imx/scu-pd.c +++ b/drivers/firmware/imx/scu-pd.c @@ -155,6 +155,10 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { { "vpu-pid", IMX_SC_R_VPU_PID0, 8, true, 0 }, { "vpu-dec0", IMX_SC_R_VPU_DEC_0, 1, false, 0 }, { "vpu-enc0", IMX_SC_R_VPU_ENC_0, 1, false, 0 }, + { "vpu-enc1", IMX_SC_R_VPU_ENC_1, 1, false, 0 }, + { "vpu-mu0", IMX_SC_R_VPU_MU_0, 1, false, 0 }, + { "vpu-mu1", IMX_SC_R_VPU_MU_1, 1, false, 0 }, + { "vpu-mu2", IMX_SC_R_VPU_MU_2, 1, false, 0 }, /* GPU SS */ { "gpu0-pid", IMX_SC_R_GPU_0_PID0, 4, true, 0 },