| Message ID | 20220124171705.10432-5-Jonathan.Cameron@huawei.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | CXl 2.0 emulation Support | expand |
Jonathan Cameron <Jonathan.Cameron@huawei.com> writes: > From: Ben Widawsky <ben.widawsky@intel.com> > > A CXL device is a type of CXL component. Conceptually, a CXL device > would be a leaf node in a CXL topology. From an emulation perspective, > CXL devices are the most complex and so the actual implementation is > reserved for discrete commits. > > This new device type is specifically catered towards the eventual > implementation of a Type3 CXL.mem device, 8.2.8.5 in the CXL 2.0 > specification. > > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > include/hw/cxl/cxl.h | 1 + > include/hw/cxl/cxl_device.h | 157 ++++++++++++++++++++++++++++++++++++ > 2 files changed, 158 insertions(+) > > diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h > index 8c738c7a2b..b9d1ac3fad 100644 > --- a/include/hw/cxl/cxl.h > +++ b/include/hw/cxl/cxl.h > @@ -12,5 +12,6 @@ > > #include "cxl_pci.h" > #include "cxl_component.h" > +#include "cxl_device.h" > > #endif > diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h > new file mode 100644 > index 0000000000..3b6ed745f0 > --- /dev/null > +++ b/include/hw/cxl/cxl_device.h > @@ -0,0 +1,157 @@ > +/* > + * QEMU CXL Devices > + * > + * Copyright (c) 2020 Intel > + * > + * This work is licensed under the terms of the GNU GPL, version 2. See the > + * COPYING file in the top-level directory. > + */ > + > +#ifndef CXL_DEVICE_H > +#define CXL_DEVICE_H > + > +#include "hw/register.h" > + > +/* > + * The following is how a CXL device's MMIO space is laid out. The only > + * requirement from the spec is that the capabilities array and the capability > + * headers start at offset 0 and are contiguously packed. The headers themselves > + * provide offsets to the register fields. For this emulation, registers will > + * start at offset 0x80 (m == 0x80). No secondary mailbox is implemented which > + * means that n = m + sizeof(mailbox registers) + sizeof(device registers). > + * > + * This is roughly described in 8.2.8 Figure 138 of the CXL 2.0 spec. > + * > + * +---------------------------------+ > + * | | > + * | Memory Device Registers | > + * | | > + * n + PAYLOAD_SIZE_MAX ----------------------------------- > + * ^ | | > + * | | | > + * | | | > + * | | | > + * | | | > + * | | Mailbox Payload | > + * | | | > + * | | | > + * | | | > + * | ----------------------------------- > + * | | Mailbox Registers | > + * | | | > + * n ----------------------------------- > + * ^ | | > + * | | Device Registers | > + * | | | > + * m ----------------------------------> > + * ^ | Memory Device Capability Header| > + * | ----------------------------------- > + * | | Mailbox Capability Header | > + * | -------------- -------------------- > + * | | Device Capability Header | > + * | ----------------------------------- > + * | | | > + * | | | > + * | | Device Cap Array[0..n] | > + * | | | > + * | | | > + * | | > + * 0 +---------------------------------+ > + * > + */ Excellent diagram ;-) > + > +#define CXL_DEVICE_CAP_HDR1_OFFSET 0x10 /* Figure 138 */ > +#define CXL_DEVICE_CAP_REG_SIZE 0x10 /* 8.2.8.2 */ > +#define CXL_DEVICE_CAPS_MAX 4 /* 8.2.8.2.1 + 8.2.8.5 */ > + > +#define CXL_DEVICE_REGISTERS_OFFSET 0x80 /* Read comment above */ > +#define CXL_DEVICE_REGISTERS_LENGTH 0x8 /* 8.2.8.3.1 */ > + > +#define CXL_MAILBOX_REGISTERS_OFFSET \ > + (CXL_DEVICE_REGISTERS_OFFSET + CXL_DEVICE_REGISTERS_LENGTH) > +#define CXL_MAILBOX_REGISTERS_SIZE 0x20 /* 8.2.8.4, Figure 139 */ > +#define CXL_MAILBOX_PAYLOAD_SHIFT 11 > +#define CXL_MAILBOX_MAX_PAYLOAD_SIZE (1 << CXL_MAILBOX_PAYLOAD_SHIFT) > +#define CXL_MAILBOX_REGISTERS_LENGTH \ > + (CXL_MAILBOX_REGISTERS_SIZE + CXL_MAILBOX_MAX_PAYLOAD_SIZE) > + > +typedef struct cxl_device_state { > + MemoryRegion device_registers; > + > + /* mmio for device capabilities array - 8.2.8.2 */ > + MemoryRegion caps; > + > + /* mmio for the device status registers 8.2.8.3 */ > + MemoryRegion device; > + > + /* mmio for the mailbox registers 8.2.8.4 */ > + MemoryRegion mailbox; > + > + /* memory region for persistent memory, HDM */ > + uint64_t pmem_size; > +} CXLDeviceState; > + > +/* Initialize the register block for a device */ > +void cxl_device_register_block_init(Object *obj, CXLDeviceState *dev); > + > +/* Set up default values for the register block */ > +void cxl_device_register_init_common(CXLDeviceState *dev); > + > +/* CXL 2.0 - 8.2.8.1 */ > +REG32(CXL_DEV_CAP_ARRAY, 0) /* 48b!?!?! */ What does this comment mean? A 48 bit register stuffed in a 32 bit one? Doesn't seem right. > + FIELD(CXL_DEV_CAP_ARRAY, CAP_ID, 0, 16) > + FIELD(CXL_DEV_CAP_ARRAY, CAP_VERSION, 16, 8) > +REG32(CXL_DEV_CAP_ARRAY2, 4) /* We're going to pretend it's 64b */ > + FIELD(CXL_DEV_CAP_ARRAY2, CAP_COUNT, 0, 16) I'm confused why you don't treat it as a single register it is in the spec. > + > +/* > + * Helper macro to initialize capability headers for CXL devices. > + * > + * In the 8.2.8.2, this is listed as a 128b register, but in 8.2.8, it says: > + * > No registers defined in Section 8.2.8 are larger than 64-bits wide so that > + * > is the maximum access size allowed for these registers. If this rule is not > + * > followed, the behavior is undefined > + * > + * Here we've chosen to make it 4 dwords. The spec allows any pow2 multiple > + * access to be used for a register (2 qwords, 8 words, 128 bytes). > + */ > +#define CXL_DEVICE_CAPABILITY_HEADER_REGISTER(n, offset) \ > + REG32(CXL_DEV_##n##_CAP_HDR0, offset) \ > + FIELD(CXL_DEV_##n##_CAP_HDR0, CAP_ID, 0, 16) \ > + FIELD(CXL_DEV_##n##_CAP_HDR0, CAP_VERSION, 16, 8) \ > + REG32(CXL_DEV_##n##_CAP_HDR1, offset + 4) \ > + FIELD(CXL_DEV_##n##_CAP_HDR1, CAP_OFFSET, 0, 32) \ > + REG32(CXL_DEV_##n##_CAP_HDR2, offset + 8) \ > + FIELD(CXL_DEV_##n##_CAP_HDR2, CAP_LENGTH, 0, 32) > + > +CXL_DEVICE_CAPABILITY_HEADER_REGISTER(DEVICE, CXL_DEVICE_CAP_HDR1_OFFSET) > +CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MAILBOX, CXL_DEVICE_CAP_HDR1_OFFSET + \ > + CXL_DEVICE_CAP_REG_SIZE) > + > +REG32(CXL_DEV_MAILBOX_CAP, 0) > + FIELD(CXL_DEV_MAILBOX_CAP, PAYLOAD_SIZE, 0, 5) > + FIELD(CXL_DEV_MAILBOX_CAP, INT_CAP, 5, 1) > + FIELD(CXL_DEV_MAILBOX_CAP, BG_INT_CAP, 6, 1) > + FIELD(CXL_DEV_MAILBOX_CAP, MSI_N, 7, 4) > + > +REG32(CXL_DEV_MAILBOX_CTRL, 4) > + FIELD(CXL_DEV_MAILBOX_CTRL, DOORBELL, 0, 1) > + FIELD(CXL_DEV_MAILBOX_CTRL, INT_EN, 1, 1) > + FIELD(CXL_DEV_MAILBOX_CTRL, BG_INT_EN, 2, 1) > + > +/* XXX: actually a 64b register */ > +REG32(CXL_DEV_MAILBOX_STS, 0x10) > + FIELD(CXL_DEV_MAILBOX_STS, BG_OP, 0, 1) > + FIELD(CXL_DEV_MAILBOX_STS, ERRNO, 32, 16) > + FIELD(CXL_DEV_MAILBOX_STS, VENDOR_ERRNO, 48, 16) > + > +/* XXX: actually a 64b register */ > +REG32(CXL_DEV_BG_CMD_STS, 0x18) > + FIELD(CXL_DEV_BG_CMD_STS, BG, 0, 16) > + FIELD(CXL_DEV_BG_CMD_STS, DONE, 16, 7) > + FIELD(CXL_DEV_BG_CMD_STS, ERRNO, 32, 16) > + FIELD(CXL_DEV_BG_CMD_STS, VENDOR_ERRNO, 48, 16) Again is there a reason not to use REG64? I can see the need to split 128 bit registers but not 64 bit ones. > + > +REG32(CXL_DEV_CMD_PAYLOAD, 0x20) > + > +#endif Otherwise: Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
On Wed, 26 Jan 2022 18:07:40 +0000 Alex Bennée <alex.bennee@linaro.org> wrote: > Jonathan Cameron <Jonathan.Cameron@huawei.com> writes: > > > From: Ben Widawsky <ben.widawsky@intel.com> > > > > A CXL device is a type of CXL component. Conceptually, a CXL device > > would be a leaf node in a CXL topology. From an emulation perspective, > > CXL devices are the most complex and so the actual implementation is > > reserved for discrete commits. > > > > This new device type is specifically catered towards the eventual > > implementation of a Type3 CXL.mem device, 8.2.8.5 in the CXL 2.0 > > specification. > > > > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> > > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > > --- > > include/hw/cxl/cxl.h | 1 + > > include/hw/cxl/cxl_device.h | 157 ++++++++++++++++++++++++++++++++++++ > > 2 files changed, 158 insertions(+) > > > > diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h > > index 8c738c7a2b..b9d1ac3fad 100644 > > --- a/include/hw/cxl/cxl.h > > +++ b/include/hw/cxl/cxl.h > > @@ -12,5 +12,6 @@ > > > > #include "cxl_pci.h" > > #include "cxl_component.h" > > +#include "cxl_device.h" > > > > #endif > > diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h > > new file mode 100644 > > index 0000000000..3b6ed745f0 > > --- /dev/null > > +++ b/include/hw/cxl/cxl_device.h > > @@ -0,0 +1,157 @@ > > +/* > > + * QEMU CXL Devices > > + * > > + * Copyright (c) 2020 Intel > > + * > > + * This work is licensed under the terms of the GNU GPL, version 2. See the > > + * COPYING file in the top-level directory. > > + */ > > + > > +#ifndef CXL_DEVICE_H > > +#define CXL_DEVICE_H > > + > > +#include "hw/register.h" > > + > > +/* > > + * The following is how a CXL device's MMIO space is laid out. The only > > + * requirement from the spec is that the capabilities array and the capability > > + * headers start at offset 0 and are contiguously packed. The headers themselves > > + * provide offsets to the register fields. For this emulation, registers will > > + * start at offset 0x80 (m == 0x80). No secondary mailbox is implemented which > > + * means that n = m + sizeof(mailbox registers) + sizeof(device registers). > > + * > > + * This is roughly described in 8.2.8 Figure 138 of the CXL 2.0 spec. > > + * > > + * +---------------------------------+ > > + * | | > > + * | Memory Device Registers | > > + * | | > > + * n + PAYLOAD_SIZE_MAX ----------------------------------- > > + * ^ | | > > + * | | | > > + * | | | > > + * | | | > > + * | | | > > + * | | Mailbox Payload | > > + * | | | > > + * | | | > > + * | | | > > + * | ----------------------------------- > > + * | | Mailbox Registers | > > + * | | | > > + * n ----------------------------------- > > + * ^ | | > > + * | | Device Registers | > > + * | | | > > + * m ----------------------------------> > > + * ^ | Memory Device Capability Header| > > + * | ----------------------------------- > > + * | | Mailbox Capability Header | > > + * | -------------- -------------------- > > + * | | Device Capability Header | > > + * | ----------------------------------- > > + * | | | > > + * | | | > > + * | | Device Cap Array[0..n] | > > + * | | | > > + * | | | > > + * | | > > + * 0 +---------------------------------+ > > + * > > + */ > > Excellent diagram ;-) > > > + > > +#define CXL_DEVICE_CAP_HDR1_OFFSET 0x10 /* Figure 138 */ > > +#define CXL_DEVICE_CAP_REG_SIZE 0x10 /* 8.2.8.2 */ > > +#define CXL_DEVICE_CAPS_MAX 4 /* 8.2.8.2.1 + 8.2.8.5 */ > > + > > +#define CXL_DEVICE_REGISTERS_OFFSET 0x80 /* Read comment above */ > > +#define CXL_DEVICE_REGISTERS_LENGTH 0x8 /* 8.2.8.3.1 */ > > + > > +#define CXL_MAILBOX_REGISTERS_OFFSET \ > > + (CXL_DEVICE_REGISTERS_OFFSET + CXL_DEVICE_REGISTERS_LENGTH) > > +#define CXL_MAILBOX_REGISTERS_SIZE 0x20 /* 8.2.8.4, Figure 139 */ > > +#define CXL_MAILBOX_PAYLOAD_SHIFT 11 > > +#define CXL_MAILBOX_MAX_PAYLOAD_SIZE (1 << CXL_MAILBOX_PAYLOAD_SHIFT) > > +#define CXL_MAILBOX_REGISTERS_LENGTH \ > > + (CXL_MAILBOX_REGISTERS_SIZE + CXL_MAILBOX_MAX_PAYLOAD_SIZE) > > + > > +typedef struct cxl_device_state { > > + MemoryRegion device_registers; > > + > > + /* mmio for device capabilities array - 8.2.8.2 */ > > + MemoryRegion caps; > > + > > + /* mmio for the device status registers 8.2.8.3 */ > > + MemoryRegion device; > > + > > + /* mmio for the mailbox registers 8.2.8.4 */ > > + MemoryRegion mailbox; > > + > > + /* memory region for persistent memory, HDM */ > > + uint64_t pmem_size; > > +} CXLDeviceState; > > + > > +/* Initialize the register block for a device */ > > +void cxl_device_register_block_init(Object *obj, CXLDeviceState *dev); > > + > > +/* Set up default values for the register block */ > > +void cxl_device_register_init_common(CXLDeviceState *dev); > > + > > +/* CXL 2.0 - 8.2.8.1 */ > > +REG32(CXL_DEV_CAP_ARRAY, 0) /* 48b!?!?! */ > > What does this comment mean? A 48 bit register stuffed in a 32 bit one? > Doesn't seem right. ah. I'd forgotten about this.. !?!?! is code word for spec bug without actually saying it in a public email... It's fixed now in the published errata which makes this a 128bit register but then says you can access it as a 64 bit register and reserves everything above bit 48. I'll update the comment and make it a REG64. > > > + FIELD(CXL_DEV_CAP_ARRAY, CAP_ID, 0, 16) > > + FIELD(CXL_DEV_CAP_ARRAY, CAP_VERSION, 16, 8) > > +REG32(CXL_DEV_CAP_ARRAY2, 4) /* We're going to pretend it's 64b */ > > + FIELD(CXL_DEV_CAP_ARRAY2, CAP_COUNT, 0, 16) > > I'm confused why you don't treat it as a single register it is in the > spec. Code predates introduction of REG64() and I'd missed that turning up. > > > + > > +/* > > + * Helper macro to initialize capability headers for CXL devices. > > + * > > + * In the 8.2.8.2, this is listed as a 128b register, but in 8.2.8, it says: > > + * > No registers defined in Section 8.2.8 are larger than 64-bits wide so that > > + * > is the maximum access size allowed for these registers. If this rule is not > > + * > followed, the behavior is undefined > > + * > > + * Here we've chosen to make it 4 dwords. The spec allows any pow2 multiple > > + * access to be used for a register (2 qwords, 8 words, 128 bytes). The F4 errata covers this as well, making it clear that 128bit registers can be accessed as 1,2,4,8 byte aligned reads. No read advantage of REG64 over REG32 as neither matches the spec, so I'll leave this one alone but update the comment.. > > + */ > > +#define CXL_DEVICE_CAPABILITY_HEADER_REGISTER(n, offset) \ > > + REG32(CXL_DEV_##n##_CAP_HDR0, offset) \ > > + FIELD(CXL_DEV_##n##_CAP_HDR0, CAP_ID, 0, 16) \ > > + FIELD(CXL_DEV_##n##_CAP_HDR0, CAP_VERSION, 16, 8) \ > > + REG32(CXL_DEV_##n##_CAP_HDR1, offset + 4) \ > > + FIELD(CXL_DEV_##n##_CAP_HDR1, CAP_OFFSET, 0, 32) \ > > + REG32(CXL_DEV_##n##_CAP_HDR2, offset + 8) \ > > + FIELD(CXL_DEV_##n##_CAP_HDR2, CAP_LENGTH, 0, 32) > > + > > +CXL_DEVICE_CAPABILITY_HEADER_REGISTER(DEVICE, CXL_DEVICE_CAP_HDR1_OFFSET) > > +CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MAILBOX, CXL_DEVICE_CAP_HDR1_OFFSET + \ > > + CXL_DEVICE_CAP_REG_SIZE) > > + > > +REG32(CXL_DEV_MAILBOX_CAP, 0) > > + FIELD(CXL_DEV_MAILBOX_CAP, PAYLOAD_SIZE, 0, 5) > > + FIELD(CXL_DEV_MAILBOX_CAP, INT_CAP, 5, 1) > > + FIELD(CXL_DEV_MAILBOX_CAP, BG_INT_CAP, 6, 1) > > + FIELD(CXL_DEV_MAILBOX_CAP, MSI_N, 7, 4) > > + > > +REG32(CXL_DEV_MAILBOX_CTRL, 4) > > + FIELD(CXL_DEV_MAILBOX_CTRL, DOORBELL, 0, 1) > > + FIELD(CXL_DEV_MAILBOX_CTRL, INT_EN, 1, 1) > > + FIELD(CXL_DEV_MAILBOX_CTRL, BG_INT_EN, 2, 1) > > + > > +/* XXX: actually a 64b register */ > > +REG32(CXL_DEV_MAILBOX_STS, 0x10) > > + FIELD(CXL_DEV_MAILBOX_STS, BG_OP, 0, 1) > > + FIELD(CXL_DEV_MAILBOX_STS, ERRNO, 32, 16) > > + FIELD(CXL_DEV_MAILBOX_STS, VENDOR_ERRNO, 48, 16) > > + > > +/* XXX: actually a 64b register */ > > +REG32(CXL_DEV_BG_CMD_STS, 0x18) > > + FIELD(CXL_DEV_BG_CMD_STS, BG, 0, 16) > > + FIELD(CXL_DEV_BG_CMD_STS, DONE, 16, 7) > > + FIELD(CXL_DEV_BG_CMD_STS, ERRNO, 32, 16) > > + FIELD(CXL_DEV_BG_CMD_STS, VENDOR_ERRNO, 48, 16) > > Again is there a reason not to use REG64? I can see the need to split > 128 bit registers but not 64 bit ones. Will do. > > > + > > +REG32(CXL_DEV_CMD_PAYLOAD, 0x20) > > + > > +#endif > > Otherwise: > > Reviewed-by: Alex Bennée <alex.bennee@linaro.org> >
diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h index 8c738c7a2b..b9d1ac3fad 100644 --- a/include/hw/cxl/cxl.h +++ b/include/hw/cxl/cxl.h @@ -12,5 +12,6 @@ #include "cxl_pci.h" #include "cxl_component.h" +#include "cxl_device.h" #endif diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h new file mode 100644 index 0000000000..3b6ed745f0 --- /dev/null +++ b/include/hw/cxl/cxl_device.h @@ -0,0 +1,157 @@ +/* + * QEMU CXL Devices + * + * Copyright (c) 2020 Intel + * + * This work is licensed under the terms of the GNU GPL, version 2. See the + * COPYING file in the top-level directory. + */ + +#ifndef CXL_DEVICE_H +#define CXL_DEVICE_H + +#include "hw/register.h" + +/* + * The following is how a CXL device's MMIO space is laid out. The only + * requirement from the spec is that the capabilities array and the capability + * headers start at offset 0 and are contiguously packed. The headers themselves + * provide offsets to the register fields. For this emulation, registers will + * start at offset 0x80 (m == 0x80). No secondary mailbox is implemented which + * means that n = m + sizeof(mailbox registers) + sizeof(device registers). + * + * This is roughly described in 8.2.8 Figure 138 of the CXL 2.0 spec. + * + * +---------------------------------+ + * | | + * | Memory Device Registers | + * | | + * n + PAYLOAD_SIZE_MAX ----------------------------------- + * ^ | | + * | | | + * | | | + * | | | + * | | | + * | | Mailbox Payload | + * | | | + * | | | + * | | | + * | ----------------------------------- + * | | Mailbox Registers | + * | | | + * n ----------------------------------- + * ^ | | + * | | Device Registers | + * | | | + * m ----------------------------------> + * ^ | Memory Device Capability Header| + * | ----------------------------------- + * | | Mailbox Capability Header | + * | -------------- -------------------- + * | | Device Capability Header | + * | ----------------------------------- + * | | | + * | | | + * | | Device Cap Array[0..n] | + * | | | + * | | | + * | | + * 0 +---------------------------------+ + * + */ + +#define CXL_DEVICE_CAP_HDR1_OFFSET 0x10 /* Figure 138 */ +#define CXL_DEVICE_CAP_REG_SIZE 0x10 /* 8.2.8.2 */ +#define CXL_DEVICE_CAPS_MAX 4 /* 8.2.8.2.1 + 8.2.8.5 */ + +#define CXL_DEVICE_REGISTERS_OFFSET 0x80 /* Read comment above */ +#define CXL_DEVICE_REGISTERS_LENGTH 0x8 /* 8.2.8.3.1 */ + +#define CXL_MAILBOX_REGISTERS_OFFSET \ + (CXL_DEVICE_REGISTERS_OFFSET + CXL_DEVICE_REGISTERS_LENGTH) +#define CXL_MAILBOX_REGISTERS_SIZE 0x20 /* 8.2.8.4, Figure 139 */ +#define CXL_MAILBOX_PAYLOAD_SHIFT 11 +#define CXL_MAILBOX_MAX_PAYLOAD_SIZE (1 << CXL_MAILBOX_PAYLOAD_SHIFT) +#define CXL_MAILBOX_REGISTERS_LENGTH \ + (CXL_MAILBOX_REGISTERS_SIZE + CXL_MAILBOX_MAX_PAYLOAD_SIZE) + +typedef struct cxl_device_state { + MemoryRegion device_registers; + + /* mmio for device capabilities array - 8.2.8.2 */ + MemoryRegion caps; + + /* mmio for the device status registers 8.2.8.3 */ + MemoryRegion device; + + /* mmio for the mailbox registers 8.2.8.4 */ + MemoryRegion mailbox; + + /* memory region for persistent memory, HDM */ + uint64_t pmem_size; +} CXLDeviceState; + +/* Initialize the register block for a device */ +void cxl_device_register_block_init(Object *obj, CXLDeviceState *dev); + +/* Set up default values for the register block */ +void cxl_device_register_init_common(CXLDeviceState *dev); + +/* CXL 2.0 - 8.2.8.1 */ +REG32(CXL_DEV_CAP_ARRAY, 0) /* 48b!?!?! */ + FIELD(CXL_DEV_CAP_ARRAY, CAP_ID, 0, 16) + FIELD(CXL_DEV_CAP_ARRAY, CAP_VERSION, 16, 8) +REG32(CXL_DEV_CAP_ARRAY2, 4) /* We're going to pretend it's 64b */ + FIELD(CXL_DEV_CAP_ARRAY2, CAP_COUNT, 0, 16) + +/* + * Helper macro to initialize capability headers for CXL devices. + * + * In the 8.2.8.2, this is listed as a 128b register, but in 8.2.8, it says: + * > No registers defined in Section 8.2.8 are larger than 64-bits wide so that + * > is the maximum access size allowed for these registers. If this rule is not + * > followed, the behavior is undefined + * + * Here we've chosen to make it 4 dwords. The spec allows any pow2 multiple + * access to be used for a register (2 qwords, 8 words, 128 bytes). + */ +#define CXL_DEVICE_CAPABILITY_HEADER_REGISTER(n, offset) \ + REG32(CXL_DEV_##n##_CAP_HDR0, offset) \ + FIELD(CXL_DEV_##n##_CAP_HDR0, CAP_ID, 0, 16) \ + FIELD(CXL_DEV_##n##_CAP_HDR0, CAP_VERSION, 16, 8) \ + REG32(CXL_DEV_##n##_CAP_HDR1, offset + 4) \ + FIELD(CXL_DEV_##n##_CAP_HDR1, CAP_OFFSET, 0, 32) \ + REG32(CXL_DEV_##n##_CAP_HDR2, offset + 8) \ + FIELD(CXL_DEV_##n##_CAP_HDR2, CAP_LENGTH, 0, 32) + +CXL_DEVICE_CAPABILITY_HEADER_REGISTER(DEVICE, CXL_DEVICE_CAP_HDR1_OFFSET) +CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MAILBOX, CXL_DEVICE_CAP_HDR1_OFFSET + \ + CXL_DEVICE_CAP_REG_SIZE) + +REG32(CXL_DEV_MAILBOX_CAP, 0) + FIELD(CXL_DEV_MAILBOX_CAP, PAYLOAD_SIZE, 0, 5) + FIELD(CXL_DEV_MAILBOX_CAP, INT_CAP, 5, 1) + FIELD(CXL_DEV_MAILBOX_CAP, BG_INT_CAP, 6, 1) + FIELD(CXL_DEV_MAILBOX_CAP, MSI_N, 7, 4) + +REG32(CXL_DEV_MAILBOX_CTRL, 4) + FIELD(CXL_DEV_MAILBOX_CTRL, DOORBELL, 0, 1) + FIELD(CXL_DEV_MAILBOX_CTRL, INT_EN, 1, 1) + FIELD(CXL_DEV_MAILBOX_CTRL, BG_INT_EN, 2, 1) + +/* XXX: actually a 64b register */ +REG32(CXL_DEV_MAILBOX_STS, 0x10) + FIELD(CXL_DEV_MAILBOX_STS, BG_OP, 0, 1) + FIELD(CXL_DEV_MAILBOX_STS, ERRNO, 32, 16) + FIELD(CXL_DEV_MAILBOX_STS, VENDOR_ERRNO, 48, 16) + +/* XXX: actually a 64b register */ +REG32(CXL_DEV_BG_CMD_STS, 0x18) + FIELD(CXL_DEV_BG_CMD_STS, BG, 0, 16) + FIELD(CXL_DEV_BG_CMD_STS, DONE, 16, 7) + FIELD(CXL_DEV_BG_CMD_STS, ERRNO, 32, 16) + FIELD(CXL_DEV_BG_CMD_STS, VENDOR_ERRNO, 48, 16) + +REG32(CXL_DEV_CMD_PAYLOAD, 0x20) + +#endif