Message ID | 20220127015857.9868-7-biao.huang@mediatek.com (mailing list archive) |
---|---|
State | Not Applicable |
Delegated to: | Netdev Maintainers |
Headers | show |
Series | add more features for mtk-star-emac | expand |
Context | Check | Description |
---|---|---|
netdev/tree_selection | success | Clearly marked for net-next |
netdev/apply | fail | Patch does not apply to net-next |
On 1/27/22 9:58 AM, Biao Huang wrote: > Add simple clock inversion for timing adjustment in driver. > Add property "mediatek,txc-inverse" or "mediatek,rxc-inverse" to > device node when necessary. > > Signed-off-by: Biao Huang <biao.huang@mediatek.com> > Signed-off-by: Yinghua Pan <ot_yinghua.pan@mediatek.com> > --- > drivers/net/ethernet/mediatek/mtk_star_emac.c | 34 +++++++++++++++++++ > 1 file changed, 34 insertions(+) > > diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/ethernet/mediatek/mtk_star_emac.c > index d69f75661e75..d5e974e0db6d 100644 > --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c > +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c > @@ -131,6 +131,11 @@ static const char *const mtk_star_clk_names[] = { "core", "reg", "trans" }; > #define MTK_STAR_REG_INT_MASK 0x0054 > #define MTK_STAR_BIT_INT_MASK_FNRC BIT(6) > > +/* Delay-Macro Register */ > +#define MTK_STAR_REG_TEST0 0x0058 > +#define MTK_STAR_BIT_INV_RX_CLK BIT(30) > +#define MTK_STAR_BIT_INV_TX_CLK BIT(31) > + > /* Misc. Config Register */ > #define MTK_STAR_REG_TEST1 0x005c > #define MTK_STAR_BIT_TEST1_RST_HASH_MBIST BIT(31) > @@ -268,6 +273,8 @@ struct mtk_star_priv { > int duplex; > int pause; > bool rmii_rxc; > + bool rx_inv; > + bool tx_inv; > > const struct mtk_star_compat *compat_data; > > @@ -1450,6 +1457,25 @@ static void mtk_star_clk_disable_unprepare(void *data) > clk_bulk_disable_unprepare(MTK_STAR_NCLKS, priv->clks); > } > > +static int mtk_star_set_timing(struct mtk_star_priv *priv) > +{ > + struct device *dev = mtk_star_get_dev(priv); > + unsigned int delay_val = 0; > + > + switch (priv->phy_intf) { > + case PHY_INTERFACE_MODE_RMII: > + delay_val |= FIELD_PREP(MTK_STAR_BIT_INV_RX_CLK, priv->rx_inv); > + delay_val |= FIELD_PREP(MTK_STAR_BIT_INV_TX_CLK, priv->tx_inv); > + break; > + default: > + dev_err(dev, "This interface not supported\n"); > + return -EINVAL; > + } > + > + regmap_write(priv->regs, MTK_STAR_REG_TEST0, delay_val); > + > + return 0; > +} > static int mtk_star_probe(struct platform_device *pdev) > { > struct device_node *of_node; > @@ -1532,6 +1558,8 @@ static int mtk_star_probe(struct platform_device *pdev) > } > > priv->rmii_rxc = of_property_read_bool(of_node, "mediatek,rmii-rxc"); > + priv->rx_inv = of_property_read_bool(of_node, "mediatek,rxc-inverse"); > + priv->tx_inv = of_property_read_bool(of_node, "mediatek,txc-inverse"); > > if (priv->compat_data->set_interface_mode) { > ret = priv->compat_data->set_interface_mode(ndev); > @@ -1541,6 +1569,12 @@ static int mtk_star_probe(struct platform_device *pdev) > } > } > > + ret = mtk_star_set_timing(priv); > + if (ret) { > + dev_err(dev, "Failed to set timing, err = %d\n", ret); > + return -EINVAL; > + } > + > ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); > if (ret) { > dev_err(dev, "unsupported DMA mask\n"); > Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com> Regards, Macpaul Lin
diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/ethernet/mediatek/mtk_star_emac.c index d69f75661e75..d5e974e0db6d 100644 --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c @@ -131,6 +131,11 @@ static const char *const mtk_star_clk_names[] = { "core", "reg", "trans" }; #define MTK_STAR_REG_INT_MASK 0x0054 #define MTK_STAR_BIT_INT_MASK_FNRC BIT(6) +/* Delay-Macro Register */ +#define MTK_STAR_REG_TEST0 0x0058 +#define MTK_STAR_BIT_INV_RX_CLK BIT(30) +#define MTK_STAR_BIT_INV_TX_CLK BIT(31) + /* Misc. Config Register */ #define MTK_STAR_REG_TEST1 0x005c #define MTK_STAR_BIT_TEST1_RST_HASH_MBIST BIT(31) @@ -268,6 +273,8 @@ struct mtk_star_priv { int duplex; int pause; bool rmii_rxc; + bool rx_inv; + bool tx_inv; const struct mtk_star_compat *compat_data; @@ -1450,6 +1457,25 @@ static void mtk_star_clk_disable_unprepare(void *data) clk_bulk_disable_unprepare(MTK_STAR_NCLKS, priv->clks); } +static int mtk_star_set_timing(struct mtk_star_priv *priv) +{ + struct device *dev = mtk_star_get_dev(priv); + unsigned int delay_val = 0; + + switch (priv->phy_intf) { + case PHY_INTERFACE_MODE_RMII: + delay_val |= FIELD_PREP(MTK_STAR_BIT_INV_RX_CLK, priv->rx_inv); + delay_val |= FIELD_PREP(MTK_STAR_BIT_INV_TX_CLK, priv->tx_inv); + break; + default: + dev_err(dev, "This interface not supported\n"); + return -EINVAL; + } + + regmap_write(priv->regs, MTK_STAR_REG_TEST0, delay_val); + + return 0; +} static int mtk_star_probe(struct platform_device *pdev) { struct device_node *of_node; @@ -1532,6 +1558,8 @@ static int mtk_star_probe(struct platform_device *pdev) } priv->rmii_rxc = of_property_read_bool(of_node, "mediatek,rmii-rxc"); + priv->rx_inv = of_property_read_bool(of_node, "mediatek,rxc-inverse"); + priv->tx_inv = of_property_read_bool(of_node, "mediatek,txc-inverse"); if (priv->compat_data->set_interface_mode) { ret = priv->compat_data->set_interface_mode(ndev); @@ -1541,6 +1569,12 @@ static int mtk_star_probe(struct platform_device *pdev) } } + ret = mtk_star_set_timing(priv); + if (ret) { + dev_err(dev, "Failed to set timing, err = %d\n", ret); + return -EINVAL; + } + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); if (ret) { dev_err(dev, "unsupported DMA mask\n");