| Message ID | 20220121161141.14389-1-francisco.iglesias@xilinx.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Xilinx Versal's PMC SLCR and OSPI support | expand |
On Fri, 21 Jan 2022 at 16:11, Francisco Iglesias <francisco.iglesias@xilinx.com> wrote: > > Hi, > > This series attempts to add support for Xilinx Versal's PMC SLCR > (system-level control registers) and OSPI flash memory controller to > Xilinx Versal virt machine. > > The series start with adding a model of Versal's PMC SLCR and connecting > the model to the Versal virt machine. The series then adds a couple of > headers into the xlnx_csu_dma.h needed for building and reusing it later > with the OSPI. The series thereafter introduces a DMA control interface > and implements the interface in the xlnx_csu_dma for being able to reuse > and control the DMA with the OSPI controller. Thereafter a model of > Versal's OSPI controller is added and connected to the Versal virt > machine. The series then ends with adding initial support for the Micron > Xccelera mt35xu01g flash and flashes of this type are connected to the > OSPI in the Versal virt machine. Applied to target-arm.next, thanks. (I fixed the indent issue Luc noticed in patch 6.) -- PMM
On Thu, Jan 27, 2022 at 05:27:55PM +0000, Peter Maydell wrote: > On Fri, 21 Jan 2022 at 16:11, Francisco Iglesias > <francisco.iglesias@xilinx.com> wrote: > > > > Hi, > > > > This series attempts to add support for Xilinx Versal's PMC SLCR > > (system-level control registers) and OSPI flash memory controller to > > Xilinx Versal virt machine. > > > > The series start with adding a model of Versal's PMC SLCR and connecting > > the model to the Versal virt machine. The series then adds a couple of > > headers into the xlnx_csu_dma.h needed for building and reusing it later > > with the OSPI. The series thereafter introduces a DMA control interface > > and implements the interface in the xlnx_csu_dma for being able to reuse > > and control the DMA with the OSPI controller. Thereafter a model of > > Versal's OSPI controller is added and connected to the Versal virt > > machine. The series then ends with adding initial support for the Micron > > Xccelera mt35xu01g flash and flashes of this type are connected to the > > OSPI in the Versal virt machine. > > Hi Peter, > Applied to target-arm.next, thanks. (I fixed the indent issue > Luc noticed in patch 6.) Thanks a lot for above Peter! :) Also, thank you everybody for taking the time to review and providing me great feedback! Best regards, Francisco Iglesias > > -- PMM
Hi, This series attempts to add support for Xilinx Versal's PMC SLCR (system-level control registers) and OSPI flash memory controller to Xilinx Versal virt machine. The series start with adding a model of Versal's PMC SLCR and connecting the model to the Versal virt machine. The series then adds a couple of headers into the xlnx_csu_dma.h needed for building and reusing it later with the OSPI. The series thereafter introduces a DMA control interface and implements the interface in the xlnx_csu_dma for being able to reuse and control the DMA with the OSPI controller. Thereafter a model of Versal's OSPI controller is added and connected to the Versal virt machine. The series then ends with adding initial support for the Micron Xccelera mt35xu01g flash and flashes of this type are connected to the OSPI in the Versal virt machine. Best regards, Francisco Iglesias Changelog: v6 -> v7: * Remove the DMA control interface * Add a class read method to the Xilinx CSU DMA and start read transfers from OSPI model through this method (replacing the DMA control interface) v5 -> v6: * Corrected unimplemented log messages (patch: "hw/arm/xlnx-versal: Connect Versal's PMC SLCR") * Modify dma_ctrl_if_read to return a MemTxResult carrying the result of the read operation * Updated (and corrected) documentation v4 -> v5 * Use named GPIOs for "sd-emmc-sel", "qspi-ospi-mux-sel", "ospi-mux-sel" in the PMC SLCR model * Add a QEMU interface comment for the PMC SLCR model. * Switch to use OBJECT_DECLARE_SIMPLE_TYPE in both "xlnx-versal-ospi.h" and "xlnx-versal-pmc-iou-slcr.h" * Create a new patch 'or'ing the interrupts from the BBRAM and RTC model * 'Or' the interrupt from the PMC SLCR with the BBRAM and RTC interrupt inside 'xlnx-versal.c' * Connect other not yet implemented PMC SLCR GPIOs to unimplemented messages * Reworked and simplified the DMA control interface by removing the notifier and refill mechanism * Corrected various typos and grammatical errors in the DMA control interface documentation and comments * Updated the DMA control interface documentation to describe the new simplified implementation * Use ldl_le_p and ldq_le_p in the OSPI model (and remove the OSPIRdData union). Also assert in the locations that we are not overruning the new bytes buffer. * Correct the single_cs function in the OSPI model (both comment and output) * Correct a typo in a comment inside ospi_do_indirect_write (s/boundery/boundary/) * Remove an unecesary assert in the OSPI model * Add a QEMU interface comment for the OSPI model. * Rename the OSPI irq in 'xlnx-versal.c' to include 'orgate' in the name for clarifying v3 -> v4 * Correct indentation (patch: "hw/arm/xlnx-versal: Connect Versal's PMC SLCR") * Rename to include "If" in names related to the DMA control interface * In dma-ctrl-if.h: - Don't include qemu-common.h - Use DECLARE_CLASS_CHECKERS dma-ctrl.h * Add a docs/devel documentation patch for the DMA control interface * Improve git messages on the dma-ctrl-if patches v2 -> v3 * Correct and also include hw/sysbus.h and hw/register.h into xlnx_csu_dma.h (patch: "include/hw/dma/xlnx_csu_dma: Add in missing includes in the header") v1 -> v2 * Correct the reset in the PMC SLCR model * Create a sub structure for the OSPI in the Versal structure (in patch: "hw/arm/xlnx-versal: Connect the OSPI flash memory controller model") * Change to use 'drive_get' instead of 'drive_get_next' (in patch: "hw/arm/xlnx-versal-virt: Connect mt35xu01g flashes to the OSPI") * Add a maintainers patch and list myself as maintainer for the OSPI controller Francisco Iglesias (10): hw/misc: Add a model of Versal's PMC SLCR hw/arm/xlnx-versal: 'Or' the interrupts from the BBRAM and RTC models hw/arm/xlnx-versal: Connect Versal's PMC SLCR include/hw/dma/xlnx_csu_dma: Add in missing includes in the header hw/dma/xlnx_csu_dma: Support starting a read transfer through a class method hw/ssi: Add a model of Xilinx Versal's OSPI flash memory controller hw/arm/xlnx-versal: Connect the OSPI flash memory controller model hw/block/m25p80: Add support for Micron Xccela flash mt35xu01g hw/arm/xlnx-versal-virt: Connect mt35xu01g flashes to the OSPI MAINTAINERS: Add an entry for Xilinx Versal OSPI include/hw/arm/xlnx-versal.h | 30 +- include/hw/dma/xlnx_csu_dma.h | 24 +- include/hw/misc/xlnx-versal-pmc-iou-slcr.h | 78 ++ include/hw/ssi/xlnx-versal-ospi.h | 111 ++ hw/arm/xlnx-versal-virt.c | 25 +- hw/arm/xlnx-versal.c | 190 ++- hw/block/m25p80.c | 2 + hw/dma/xlnx_csu_dma.c | 17 + hw/misc/xlnx-versal-pmc-iou-slcr.c | 1446 ++++++++++++++++++++++ hw/ssi/xlnx-versal-ospi.c | 1853 ++++++++++++++++++++++++++++ MAINTAINERS | 6 + hw/misc/meson.build | 5 +- hw/ssi/meson.build | 1 + 13 files changed, 3780 insertions(+), 8 deletions(-) create mode 100644 include/hw/misc/xlnx-versal-pmc-iou-slcr.h create mode 100644 include/hw/ssi/xlnx-versal-ospi.h create mode 100644 hw/misc/xlnx-versal-pmc-iou-slcr.c create mode 100644 hw/ssi/xlnx-versal-ospi.c