| Message ID | 20220127122052.1584324-1-james.morse@arm.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | KVM: arm64: A510 errata workaround and fixes for fixup_guest_exit() | expand |
On Thu, 27 Jan 2022 12:20:48 +0000, James Morse wrote: > Changes since v1: > * Moved the SPSR_EL2 fixup into a helper called earlier > * Use final cap > * Dropped the IS_ENABLED() check Applied to fixes, thanks! [2/4] KVM: arm64: Avoid consuming a stale esr value when SError occur commit: 1c71dbc8a179d99dd9bb7e7fc1888db613cf85de [3/4] KVM: arm64: Stop handle_exit() from handling HVC twice when an SError occurs commit: 1229630af88620f6e3a621a1ebd1ca14d9340df7 [4/4] KVM: arm64: Workaround Cortex-A510's single-step and PAC trap errata commit: 1dd498e5e26ad71e3e9130daf72cfb6a693fee03 Cheers, M.
Hello! Changes since v1: * Moved the SPSR_EL2 fixup into a helper called earlier * Use final cap * Dropped the IS_ENABLED() check --- Early Cortex-A510 parts have a nasty erratum where two ERETs, pointer-auth and software step conspire to corrupt SPSR_EL2. A guest can only trigger this when it is being stepped by EL2, which gives EL2 the opportunity to work around the erratum. Patch 4 does this, the SDEN is available from: https://developer.arm.com/documentation/SDEN2397239/900 Patches 2 and 3 fix two issues with the adjacent code where a stale esr value could be used to alter the ELR_EL2 when an IRQ synchronises an SError, and when an HVC synchronises an SError, the HVC may be handled twice, (not just execute twice). There are three series that would add the Cortex-A510 part macros. I've picked Anshuman's patch that does this, on the assumption that makes someone's life easier. I haven't spotted that patch on the arm64/for-next/fixes branch, so I've not included the hash in the prerequisite field of the CC-stable. Let me know if you want this reposted once that value is known. This series is based on v5.17-rc1 and can be retrieved from: https://git.gitlab.arm.com/linux-arm/linux-jm.git a510_errata/kvm_bits/v2 Thanks, James Anshuman Khandual (1): arm64: Add Cortex-A510 CPU part definition James Morse (3): KVM: arm64: Avoid consuming a stale esr value when SError occur KVM: arm64: Stop handle_exit() from handling HVC twice when an SError occurs KVM: arm64: Workaround Cortex-A510's single-step and PAC trap errata Documentation/arm64/silicon-errata.rst | 2 ++ arch/arm64/Kconfig | 16 ++++++++++++++++ arch/arm64/include/asm/cputype.h | 2 ++ arch/arm64/kernel/cpu_errata.c | 8 ++++++++ arch/arm64/kvm/handle_exit.c | 8 ++++++++ arch/arm64/kvm/hyp/include/hyp/switch.h | 23 +++++++++++++++++++++-- arch/arm64/tools/cpucaps | 1 + 7 files changed, 58 insertions(+), 2 deletions(-)