| Message ID | 20220203115336.119735-2-james.clark@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | coresight: no-op refactor to make INSTP0 check more idiomatic | expand |
On 03/02/2022 11:53, James Clark wrote: > The spec says this: > > P0 tracing support field. The permitted values are: > 0b00 Tracing of load and store instructions as P0 elements is not > supported. > 0b11 Tracing of load and store instructions as P0 elements is > supported, so TRCCONFIGR.INSTP0 is supported. > > All other values are reserved. > > The value we are looking for is 0b11 so simplify this. The double read > and && was a bit obfuscated. > > Suggested-by: Suzuki Poulose <suzuki.poulose@arm.com> > Signed-off-by: James Clark <james.clark@arm.com> Thanks, Queued. Cheers Suzuki
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index bf18128cf5de..e2eebd865241 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1091,7 +1091,7 @@ static void etm4_init_arch_data(void *info) etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0); /* INSTP0, bits[2:1] P0 tracing support field */ - if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2)) + if (BMVAL(etmidr0, 1, 2) == 0b11) drvdata->instrp0 = true; else drvdata->instrp0 = false;
The spec says this: P0 tracing support field. The permitted values are: 0b00 Tracing of load and store instructions as P0 elements is not supported. 0b11 Tracing of load and store instructions as P0 elements is supported, so TRCCONFIGR.INSTP0 is supported. All other values are reserved. The value we are looking for is 0b11 so simplify this. The double read and && was a bit obfuscated. Suggested-by: Suzuki Poulose <suzuki.poulose@arm.com> Signed-off-by: James Clark <james.clark@arm.com> --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)