diff mbox series

[v2,2/4] arm64: cpufeature: Warn if mutually exclusive PAuth algorithms detected

Message ID 20220131170654.62381-3-vladimir.murzin@arm.com (mailing list archive)
State New, archived
Headers show
Series arm64: Support of PAuth QARMA3 architected algorithm | expand

Commit Message

Vladimir Murzin Jan. 31, 2022, 5:06 p.m. UTC
ARM ARM states for address authentication algorithms

APA, bits [7:4] If the value of ID_AA64ISAR1_EL1.API is non-zero, this
                field must have the value 0b0000.

API, bits [11:8] If the value of ID_AA64ISAR1_EL1.APA is non-zero,
                 this field must have the value 0b0000.

Similarly for generic code authentication algorithms

GPA, bits [27:24] If the value of ID_AA64ISAR1_EL1.GPI is non-zero,
                  this field must have the value 0b0000.

GPI, bits [31:28] If the value of ID_AA64ISAR1_EL1.GPA is non-zero,
                  this field must have the value 0b0000.

Let's add a warning if that not true.

Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
 arch/arm64/kernel/cpufeature.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

Comments

Catalin Marinas Feb. 4, 2022, 6:16 p.m. UTC | #1
On Mon, Jan 31, 2022 at 05:06:52PM +0000, Vladimir Murzin wrote:
> ARM ARM states for address authentication algorithms
> 
> APA, bits [7:4] If the value of ID_AA64ISAR1_EL1.API is non-zero, this
>                 field must have the value 0b0000.
> 
> API, bits [11:8] If the value of ID_AA64ISAR1_EL1.APA is non-zero,
>                  this field must have the value 0b0000.
> 
> Similarly for generic code authentication algorithms
> 
> GPA, bits [27:24] If the value of ID_AA64ISAR1_EL1.GPI is non-zero,
>                   this field must have the value 0b0000.
> 
> GPI, bits [31:28] If the value of ID_AA64ISAR1_EL1.GPA is non-zero,
>                   this field must have the value 0b0000.
> 
> Let's add a warning if that not true.
> 
> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
diff mbox series

Patch

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index b0ec125..9dad0a3 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -1832,15 +1832,23 @@  static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry,
 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry,
 				     int scope)
 {
-	return has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH], scope) ||
-	       has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope);
+	bool api = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope);
+	bool apa = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH], scope);
+
+	WARN_ON(apa && api);
+
+	return apa || api;
 }
 
 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry,
 			     int __unused)
 {
-	return __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH) ||
-	       __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF);
+	bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF);
+	bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH);
+
+	WARN_ON(gpa && gpi);
+
+	return gpa || gpi;
 }
 #endif /* CONFIG_ARM64_PTR_AUTH */