diff mbox series

[v6,6/6] drm: Add arch arm64 for drm_clflush_virt_range

Message ID 20220207201127.648624-7-michael.cheng@intel.com (mailing list archive)
State New, archived
Headers show
Series Use drm_clflush* instead of clflush | expand

Commit Message

Michael Cheng Feb. 7, 2022, 8:11 p.m. UTC 
Use flush_tlb_kernel_range when invoking drm_clflush_virt_range on
arm64 platforms. Using flush_tlb_kernel_range will:

1. Make sure prior page-table updates have been completed
2. Invalidate the TLB
3. Check if the TLB invalidation has been completed

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
 drivers/gpu/drm/drm_cache.c | 4 ++++
 1 file changed, 4 insertions(+)

Comments

kernel test robot Feb. 8, 2022, 3:51 a.m. UTC | #1 
Hi Michael,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip drm/drm-next v5.17-rc3 next-20220207]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Michael-Cheng/Use-drm_clflush-instead-of-clflush/20220208-041326
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: arm64-randconfig-r005-20220207 (https://download.01.org/0day-ci/archive/20220208/202202081151.wYD1tE4p-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 0d8850ae2cae85d49bea6ae0799fa41c7202c05c)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install arm64 cross compiling tool for clang build
        # apt-get install binutils-aarch64-linux-gnu
        # https://github.com/0day-ci/linux/commit/f2fb6ade1531d88b046e245e8b854a7422a05a14
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Michael-Cheng/Use-drm_clflush-instead-of-clflush/20220208-041326
        git checkout f2fb6ade1531d88b046e245e8b854a7422a05a14
        # save the config file to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

>> drivers/gpu/drm/drm_cache.c:182:25: error: passing 'void' to parameter of incompatible type 'unsigned long'
           flush_tlb_kernel_range(*addr, *end);
                                  ^~~~~
   arch/arm64/include/asm/tlbflush.h:374:57: note: passing argument to parameter 'start' here
   static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end)
                                                           ^
   1 error generated.


vim +182 drivers/gpu/drm/drm_cache.c

   151	
   152	/**
   153	 * drm_clflush_virt_range - Flush dcache lines of a region
   154	 * @addr: Initial kernel memory address.
   155	 * @length: Region size.
   156	 *
   157	 * Flush every data cache line entry that points to an address in the
   158	 * region requested.
   159	 */
   160	void
   161	drm_clflush_virt_range(void *addr, unsigned long length)
   162	{
   163	#if defined(CONFIG_X86)
   164		if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
   165			const int size = boot_cpu_data.x86_clflush_size;
   166			void *end = addr + length;
   167	
   168			addr = (void *)(((unsigned long)addr) & -size);
   169			mb(); /*CLFLUSH is only ordered with a full memory barrier*/
   170			for (; addr < end; addr += size)
   171				clflushopt(addr);
   172			clflushopt(end - 1); /* force serialisation */
   173			mb(); /*Ensure that every data cache line entry is flushed*/
   174			return;
   175		}
   176	
   177		if (wbinvd_on_all_cpus())
   178			pr_err("Timed out waiting for cache flush\n");
   179	
   180	#elif defined(CONFIG_ARM64)
   181		void *end = addr + length;
 > 182		flush_tlb_kernel_range(*addr, *end);
   183	#else
   184		pr_err("Architecture has no drm_cache.c support\n");
   185		WARN_ON_ONCE(1);
   186	#endif
   187	}
   188	EXPORT_SYMBOL(drm_clflush_virt_range);
   189	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
kernel test robot Feb. 8, 2022, 4:22 a.m. UTC | #2 
Hi Michael,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip drm/drm-next v5.17-rc3 next-20220207]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Michael-Cheng/Use-drm_clflush-instead-of-clflush/20220208-041326
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: arm64-defconfig (https://download.01.org/0day-ci/archive/20220208/202202081258.VY7Y7JnA-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/f2fb6ade1531d88b046e245e8b854a7422a05a14
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Michael-Cheng/Use-drm_clflush-instead-of-clflush/20220208-041326
        git checkout f2fb6ade1531d88b046e245e8b854a7422a05a14
        # save the config file to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/gpu/drm/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All error/warnings (new ones prefixed by >>):

   drivers/gpu/drm/drm_cache.c: In function 'drm_clflush_virt_range':
>> drivers/gpu/drm/drm_cache.c:182:32: warning: dereferencing 'void *' pointer
     182 |         flush_tlb_kernel_range(*addr, *end);
         |                                ^~~~~
   drivers/gpu/drm/drm_cache.c:182:39: warning: dereferencing 'void *' pointer
     182 |         flush_tlb_kernel_range(*addr, *end);
         |                                       ^~~~
>> drivers/gpu/drm/drm_cache.c:182:32: error: invalid use of void expression
     182 |         flush_tlb_kernel_range(*addr, *end);
         |                                ^~~~~
   drivers/gpu/drm/drm_cache.c:182:39: error: invalid use of void expression
     182 |         flush_tlb_kernel_range(*addr, *end);
         |                                       ^~~~


vim +182 drivers/gpu/drm/drm_cache.c

   151	
   152	/**
   153	 * drm_clflush_virt_range - Flush dcache lines of a region
   154	 * @addr: Initial kernel memory address.
   155	 * @length: Region size.
   156	 *
   157	 * Flush every data cache line entry that points to an address in the
   158	 * region requested.
   159	 */
   160	void
   161	drm_clflush_virt_range(void *addr, unsigned long length)
   162	{
   163	#if defined(CONFIG_X86)
   164		if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
   165			const int size = boot_cpu_data.x86_clflush_size;
   166			void *end = addr + length;
   167	
   168			addr = (void *)(((unsigned long)addr) & -size);
   169			mb(); /*CLFLUSH is only ordered with a full memory barrier*/
   170			for (; addr < end; addr += size)
   171				clflushopt(addr);
   172			clflushopt(end - 1); /* force serialisation */
   173			mb(); /*Ensure that every data cache line entry is flushed*/
   174			return;
   175		}
   176	
   177		if (wbinvd_on_all_cpus())
   178			pr_err("Timed out waiting for cache flush\n");
   179	
   180	#elif defined(CONFIG_ARM64)
   181		void *end = addr + length;
 > 182		flush_tlb_kernel_range(*addr, *end);
   183	#else
   184		pr_err("Architecture has no drm_cache.c support\n");
   185		WARN_ON_ONCE(1);
   186	#endif
   187	}
   188	EXPORT_SYMBOL(drm_clflush_virt_range);
   189	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
Tvrtko Ursulin Feb. 8, 2022, 10:20 a.m. UTC | #3 
On 07/02/2022 20:11, Michael Cheng wrote:
> Use flush_tlb_kernel_range when invoking drm_clflush_virt_range on
> arm64 platforms. Using flush_tlb_kernel_range will:
> 
> 1. Make sure prior page-table updates have been completed
> 2. Invalidate the TLB
> 3. Check if the TLB invalidation has been completed

Arm does not have a clflush equivalent but invalidating TLBs there 
includes flushing caches?

Regards,

Tvrtko

> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
> ---
>   drivers/gpu/drm/drm_cache.c | 4 ++++
>   1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
> index f19d9acbe959..d2506060a7c8 100644
> --- a/drivers/gpu/drm/drm_cache.c
> +++ b/drivers/gpu/drm/drm_cache.c
> @@ -176,6 +176,10 @@ drm_clflush_virt_range(void *addr, unsigned long length)
>   
>   	if (wbinvd_on_all_cpus())
>   		pr_err("Timed out waiting for cache flush\n");
> +
> +#elif defined(CONFIG_ARM64)
> +	void *end = addr + length;
> +	flush_tlb_kernel_range(*addr, *end);
>   #else
>   	pr_err("Architecture has no drm_cache.c support\n");
>   	WARN_ON_ONCE(1);
Michael Cheng Feb. 8, 2022, 3:50 p.m. UTC | #4 
Ah, thanks for asking this question. It seems like I was not thinking 
correctly. We are trying to flush dcache lines within this function and 
not the tlb.

On 2022-02-08 2:20 a.m., Tvrtko Ursulin wrote:
>
> On 07/02/2022 20:11, Michael Cheng wrote:
>> Use flush_tlb_kernel_range when invoking drm_clflush_virt_range on
>> arm64 platforms. Using flush_tlb_kernel_range will:
>>
>> 1. Make sure prior page-table updates have been completed
>> 2. Invalidate the TLB
>> 3. Check if the TLB invalidation has been completed
>
> Arm does not have a clflush equivalent but invalidating TLBs there 
> includes flushing caches?
>
> Regards,
>
> Tvrtko
>
>> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
>> ---
>>   drivers/gpu/drm/drm_cache.c | 4 ++++
>>   1 file changed, 4 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
>> index f19d9acbe959..d2506060a7c8 100644
>> --- a/drivers/gpu/drm/drm_cache.c
>> +++ b/drivers/gpu/drm/drm_cache.c
>> @@ -176,6 +176,10 @@ drm_clflush_virt_range(void *addr, unsigned long 
>> length)
>>         if (wbinvd_on_all_cpus())
>>           pr_err("Timed out waiting for cache flush\n");
>> +
>> +#elif defined(CONFIG_ARM64)
>> +    void *end = addr + length;
>> +    flush_tlb_kernel_range(*addr, *end);
>>   #else
>>       pr_err("Architecture has no drm_cache.c support\n");
>>       WARN_ON_ONCE(1);
diff mbox series

Patch

diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
index f19d9acbe959..d2506060a7c8 100644
--- a/drivers/gpu/drm/drm_cache.c
+++ b/drivers/gpu/drm/drm_cache.c
@@ -176,6 +176,10 @@  drm_clflush_virt_range(void *addr, unsigned long length)
 
 	if (wbinvd_on_all_cpus())
 		pr_err("Timed out waiting for cache flush\n");
+
+#elif defined(CONFIG_ARM64)
+	void *end = addr + length;
+	flush_tlb_kernel_range(*addr, *end);
 #else
 	pr_err("Architecture has no drm_cache.c support\n");
 	WARN_ON_ONCE(1);