| Message ID | 20220209111318.21112-1-kavyasree.kotagiri@microchip.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v4] ARM: dts: add DT for lan966 SoC and 2-port board pcb8291 | expand |
On 2/9/22 13:13, Kavyasree Kotagiri wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > This patch adds basic DT for Microchip lan966x SoC and associated board > pcb8291(2-port EVB). Adds peripherals required to allow booting: Interrupt > Controller, Clock, Generic ARMv7 Timers, Synopsys Timer, Flexcoms, GPIOs. > Also adds other peripherals like crypto(AES/SHA), DMA, Watchdog Timer, TRNG > and MCAN0. > > Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> > --- > v3 -> v4: > - Removed character 'x' from compatible string. > - Removed memory node as handled by bootloader. > - Renamed flexcom3 usart0 to usart3 > - Added /chosen and /aliases nodes in dts file. > > v2 -> v3: > - Enabling trng in dtsi itself. > - Removed "status=okay" dma0. > - Add gpio pin settings for can0(missed adding this in previous version) > > v1 -> v2: > - Moved flx3 usart0 node to dtsi file. > - Removed status="okay" for dma0 to maintain consistency across nodes > (which means enabling dma0 by default) > > arch/arm/boot/dts/Makefile | 2 + > arch/arm/boot/dts/lan966x.dtsi | 237 ++++++++++++++++++++++++++ > arch/arm/boot/dts/lan966x_pcb8291.dts | 61 +++++++ > 3 files changed, 300 insertions(+) > create mode 100644 arch/arm/boot/dts/lan966x.dtsi > create mode 100644 arch/arm/boot/dts/lan966x_pcb8291.dts > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index 235ad559acb2..2040a990f08c 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -735,6 +735,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \ > dtb-$(CONFIG_SOC_IMX7ULP) += \ > imx7ulp-com.dtb \ > imx7ulp-evk.dtb > +dtb-$(CONFIG_SOC_LAN966) += \ > + lan966x_pcb8291.dtb > dtb-$(CONFIG_SOC_LS1021A) += \ > ls1021a-moxa-uc-8410a.dtb \ > ls1021a-qds.dtb \ > diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi > new file mode 100644 > index 000000000000..91ee9e0684f4 > --- /dev/null > +++ b/arch/arm/boot/dts/lan966x.dtsi > @@ -0,0 +1,237 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC > + * > + * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries > + * > + * Author: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> > + * > + */ > + > +#include <dt-bindings/interrupt-controller/irq.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/mfd/atmel-flexcom.h> > +#include <dt-bindings/dma/at91.h> > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/clock/microchip,lan966x.h> > + > +/ { > + model = "Microchip LAN966 family SoC"; > + compatible = "microchip,lan966"; > + interrupt-parent = <&gic>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + clock-frequency = <600000000>; > + reg = <0x0>; > + }; > + }; > + > + clocks { > + sys_clk: sys_clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <162500000>; > + }; > + > + cpu_clk: cpu_clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <600000000>; > + }; > + > + ddr_clk: ddr_clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <300000000>; > + }; > + > + nic_clk: nic_clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <200000000>; > + }; > + }; > + > + clks: clock-controller@e00c00a8 { > + compatible = "microchip,lan966x-gck"; > + #clock-cells = <1>; > + clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>; > + clock-names = "cpu", "ddr", "sys"; > + reg = <0xe00c00a8 0x38>; > + }; > + > + timer { > + compatible = "arm,armv7-timer"; > + interrupt-parent = <&gic>; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; > + clock-frequency = <37500000>; > + arm,cpu-registers-not-fw-configured; > + }; > + > + soc { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + flx0: flexcom@e0040000 { > + compatible = "atmel,sama5d2-flexcom"; > + reg = <0xe0040000 0x100>; > + clocks = <&clks GCK_ID_FLEXCOM0>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0xe0040000 0x800>; > + status = "disabled"; > + }; > + > + flx1: flexcom@e0044000 { > + compatible = "atmel,sama5d2-flexcom"; > + reg = <0xe0044000 0x100>; > + clocks = <&clks GCK_ID_FLEXCOM1>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0xe0044000 0x800>; > + status = "disabled"; > + }; > + > + trng: trng@e0048000 { > + compatible = "atmel,at91sam9g45-trng"; > + reg = <0xe0048000 0x100>; > + clocks = <&nic_clk>; > + }; > + > + aes: aes@e004c000 { Use generic names for nodes, so that we follow the dt node name recommendation. Use aes: crypto@e004c000. you can find dt specification at https://github.com/devicetree-org/devicetree-specification/releases/tag/v0.4-rc1 You can check https://lore.kernel.org/lkml/20220208111225.234685-1-tudor.ambarus@microchip.com/ for reference. Also, please check other node names as well. On a quick look "trng" should be replaced with "rng". cheers, ta
Hi, > + clocks { [..] > + > + nic_clk: nic_clk { What does nic_clk stand for? If I had to guess, it has something to do with network. But.. > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <200000000>; > + }; > + }; > + > + clks: clock-controller@e00c00a8 { > + compatible = "microchip,lan966x-gck"; > + #clock-cells = <1>; > + clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>; > + clock-names = "cpu", "ddr", "sys"; > + reg = <0xe00c00a8 0x38>; > + }; > + > + timer { > + compatible = "arm,armv7-timer"; > + interrupt-parent = <&gic>; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; > + clock-frequency = <37500000>; > + arm,cpu-registers-not-fw-configured; > + }; > + > + soc { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + flx0: flexcom@e0040000 { > + compatible = "atmel,sama5d2-flexcom"; > + reg = <0xe0040000 0x100>; > + clocks = <&clks GCK_ID_FLEXCOM0>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0xe0040000 0x800>; > + status = "disabled"; > + }; > + > + flx1: flexcom@e0044000 { > + compatible = "atmel,sama5d2-flexcom"; > + reg = <0xe0044000 0x100>; > + clocks = <&clks GCK_ID_FLEXCOM1>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0xe0044000 0x800>; > + status = "disabled"; > + }; > + > + trng: trng@e0048000 { > + compatible = "atmel,at91sam9g45-trng"; > + reg = <0xe0048000 0x100>; > + clocks = <&nic_clk>; .. it is used here.. > + }; > + > + aes: aes@e004c000 { > + compatible = "atmel,at91sam9g46-aes"; > + reg = <0xe004c000 0x100>; > + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&dma0 AT91_XDMAC_DT_PERID(13)>, > + <&dma0 AT91_XDMAC_DT_PERID(12)>; > + dma-names = "rx", "tx"; > + clocks = <&nic_clk>; .. and here. and so on. So, is it some kind of internal clock? > + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + watchdog: watchdog@e0090000 { > + compatible = "snps,dw-wdt"; > + reg = <0xe0090000 0x1000>; > + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&nic_clk>; Btw. can we disable all nodes by default and enable them in the board dts files?
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > Hi, > > > + clocks { > [..] > > + > > + nic_clk: nic_clk { > > What does nic_clk stand for? If I had to guess, it > has something to do with network. But.. > NIC clock is the clock used by AXI, AHB fabric and APB bridges which connects all the peripherals. It is named so because the AXI fabric is based on NIC400 IP from ARM > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <200000000>; > > + }; > > + }; > > + > > + clks: clock-controller@e00c00a8 { > > + compatible = "microchip,lan966x-gck"; > > + #clock-cells = <1>; > > + clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>; > > + clock-names = "cpu", "ddr", "sys"; > > + reg = <0xe00c00a8 0x38>; > > + }; > > + > > + timer { > > + compatible = "arm,armv7-timer"; > > + interrupt-parent = <&gic>; > > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | > IRQ_TYPE_LEVEL_LOW)>, > > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | > IRQ_TYPE_LEVEL_LOW)>, > > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | > IRQ_TYPE_LEVEL_LOW)>, > > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | > IRQ_TYPE_LEVEL_LOW)>; > > + clock-frequency = <37500000>; > > + arm,cpu-registers-not-fw-configured; > > + }; > > + > > + soc { > > + compatible = "simple-bus"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges; > > + > > + flx0: flexcom@e0040000 { > > + compatible = "atmel,sama5d2-flexcom"; > > + reg = <0xe0040000 0x100>; > > + clocks = <&clks GCK_ID_FLEXCOM0>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges = <0x0 0xe0040000 0x800>; > > + status = "disabled"; > > + }; > > + > > + flx1: flexcom@e0044000 { > > + compatible = "atmel,sama5d2-flexcom"; > > + reg = <0xe0044000 0x100>; > > + clocks = <&clks GCK_ID_FLEXCOM1>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges = <0x0 0xe0044000 0x800>; > > + status = "disabled"; > > + }; > > + > > + trng: trng@e0048000 { > > + compatible = "atmel,at91sam9g45-trng"; > > + reg = <0xe0048000 0x100>; > > + clocks = <&nic_clk>; > > .. it is used here.. > > > > + }; > > + > > + aes: aes@e004c000 { > > + compatible = "atmel,at91sam9g46-aes"; > > + reg = <0xe004c000 0x100>; > > + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; > > + dmas = <&dma0 AT91_XDMAC_DT_PERID(13)>, > > + <&dma0 AT91_XDMAC_DT_PERID(12)>; > > + dma-names = "rx", "tx"; > > + clocks = <&nic_clk>; > > .. and here. and so on. > > So, is it some kind of internal clock? > > > + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + > > + watchdog: watchdog@e0090000 { > > + compatible = "snps,dw-wdt"; > > + reg = <0xe0090000 0x1000>; > > + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&nic_clk>; > > Btw. can we disable all nodes by default and enable them > in the board dts files? I would like to have only board specific nodes enabled in dts files and rest of them in dtsi file Thanks, Kavya
Am 2022-02-10 10:40, schrieb Kavyasree.Kotagiri@microchip.com: >> EXTERNAL EMAIL: Do not click links or open attachments unless you know >> the >> content is safe >> > + clocks { >> [..] >> > + >> > + nic_clk: nic_clk { >> >> What does nic_clk stand for? If I had to guess, it >> has something to do with network. But.. >> > NIC clock is the clock used by AXI, AHB fabric and APB bridges which > connects all the peripherals. > It is named so because the AXI fabric is based on NIC400 IP from ARM Ok, thanks for clarification. >> > + watchdog: watchdog@e0090000 { >> > + compatible = "snps,dw-wdt"; >> > + reg = <0xe0090000 0x1000>; >> > + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; >> > + clocks = <&nic_clk>; >> >> Btw. can we disable all nodes by default and enable them >> in the board dts files? > I would like to have only board specific nodes enabled in dts files > and rest of them in dtsi file And how do you know which ones are board specific? E.g. I would like to add our board which is also based on the lan9668. Maybe I don't want a watchdog (or whatever node). Of course I could use &watchdog { status = "disabled"; }; But IMHO opt-in is better. At least thats what we are doing for the layerscape over on arm64. -michael
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > Am 2022-02-10 10:40, schrieb Kavyasree.Kotagiri@microchip.com: > >> EXTERNAL EMAIL: Do not click links or open attachments unless you know > >> the > >> content is safe > > >> > + clocks { > >> [..] > >> > + > >> > + nic_clk: nic_clk { > >> > >> What does nic_clk stand for? If I had to guess, it > >> has something to do with network. But.. > >> > > NIC clock is the clock used by AXI, AHB fabric and APB bridges which > > connects all the peripherals. > > It is named so because the AXI fabric is based on NIC400 IP from ARM > > Ok, thanks for clarification. > > > >> > + watchdog: watchdog@e0090000 { > >> > + compatible = "snps,dw-wdt"; > >> > + reg = <0xe0090000 0x1000>; > >> > + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; > >> > + clocks = <&nic_clk>; > >> > >> Btw. can we disable all nodes by default and enable them > >> in the board dts files? > > I would like to have only board specific nodes enabled in dts files > > and rest of them in dtsi file > > And how do you know which ones are board specific? E.g. I would like > to add our board which is also based on the lan9668. Maybe I don't > want a watchdog (or whatever node). Of course I could use > > &watchdog { > status = "disabled"; > }; > > But IMHO opt-in is better. At least thats what we are doing for > the layerscape over on arm64. > Basically, I am disabling only the nodes which have pinctrl settings in dtsi file and enable in dts to make sure there are no conflicts on pins on the board. > -michael
Am 2022-02-10 12:52, schrieb Kavyasree.Kotagiri@microchip.com: >> EXTERNAL EMAIL: Do not click links or open attachments unless you know >> the >> content is safe >> >> Am 2022-02-10 10:40, schrieb Kavyasree.Kotagiri@microchip.com: >> >> EXTERNAL EMAIL: Do not click links or open attachments unless you know >> >> the >> >> content is safe >> >> >> > + clocks { >> >> [..] >> >> > + >> >> > + nic_clk: nic_clk { >> >> >> >> What does nic_clk stand for? If I had to guess, it >> >> has something to do with network. But.. >> >> >> > NIC clock is the clock used by AXI, AHB fabric and APB bridges which >> > connects all the peripherals. >> > It is named so because the AXI fabric is based on NIC400 IP from ARM >> >> Ok, thanks for clarification. >> >> >> >> > + watchdog: watchdog@e0090000 { >> >> > + compatible = "snps,dw-wdt"; >> >> > + reg = <0xe0090000 0x1000>; >> >> > + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; >> >> > + clocks = <&nic_clk>; >> >> >> >> Btw. can we disable all nodes by default and enable them >> >> in the board dts files? >> > I would like to have only board specific nodes enabled in dts files >> > and rest of them in dtsi file >> >> And how do you know which ones are board specific? E.g. I would like >> to add our board which is also based on the lan9668. Maybe I don't >> want a watchdog (or whatever node). Of course I could use >> >> &watchdog { >> status = "disabled"; >> }; >> >> But IMHO opt-in is better. At least thats what we are doing for >> the layerscape over on arm64. >> > Basically, I am disabling only the nodes which have pinctrl settings > in dtsi file > and enable in dts to make sure there are no conflicts on pins on the > board. Thats not what I'm asking. I would like to see *optional* nodes disabled by default. Whether the watchdog is optional might be debatable, but what about the usb controller and the qspi controller? They don't have shared pins AFAIK, so according to your rule, they will be enabled by default and each board which doesn't have anything connected on these pins would have to disabled it. Please keep in mind that this .dtsi will also be used by boards not manufactured by microchip. -michael
Hi, > arch/arm/boot/dts/Makefile | 2 + > arch/arm/boot/dts/lan966x.dtsi | 237 ++++++++++++++++++++++++++ > arch/arm/boot/dts/lan966x_pcb8291.dts | 61 +++++++ Please rename this to lan966x-pcb8921.dts. All (most?) of the device tree files use the dash as a seperator between the SoC and the board. > diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi > new file mode 100644 > index 000000000000..91ee9e0684f4 > --- /dev/null > +++ b/arch/arm/boot/dts/lan966x.dtsi > @@ -0,0 +1,237 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC > + * > + * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries > + * > + * Author: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> > + * > + */ > + > +#include <dt-bindings/interrupt-controller/irq.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/mfd/atmel-flexcom.h> > +#include <dt-bindings/dma/at91.h> > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/clock/microchip,lan966x.h> > + > +/ { > + model = "Microchip LAN966 family SoC"; > + compatible = "microchip,lan966"; Undocumented compatible string. I see that the actual board is documented in Documentation/devicetree/bindings/arm/atmel-at91.yaml But as Arnd mentioned, this doesn't really make sense here as you have to override it in the actual board dts anyway. > + interrupt-parent = <&gic>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + clock-frequency = <600000000>; > + reg = <0x0>; > + }; > + }; > + > + clocks { > + sys_clk: sys_clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <162500000>; > + }; > + > + cpu_clk: cpu_clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <600000000>; > + }; > + > + ddr_clk: ddr_clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <300000000>; > + }; > + > + nic_clk: nic_clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <200000000>; > + }; > + }; > + > + clks: clock-controller@e00c00a8 { > + compatible = "microchip,lan966x-gck"; > + #clock-cells = <1>; > + clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>; > + clock-names = "cpu", "ddr", "sys"; > + reg = <0xe00c00a8 0x38>; > + }; > + > + timer { > + compatible = "arm,armv7-timer"; > + interrupt-parent = <&gic>; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; > + clock-frequency = <37500000>; > + arm,cpu-registers-not-fw-configured; > + }; > + > + soc { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + flx0: flexcom@e0040000 { > + compatible = "atmel,sama5d2-flexcom"; Are these expected to be exactly the same between the lan966x and the sama5d2 or do you need something like compatible = "microchip,lan966x-flexcom", "atmel,sama5d2-flexcom"; for the case when you need to make SoC specific settings/workarounds? > + reg = <0xe0040000 0x100>; > + clocks = <&clks GCK_ID_FLEXCOM0>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0xe0040000 0x800>; > + status = "disabled"; > + }; > + > + flx1: flexcom@e0044000 { > + compatible = "atmel,sama5d2-flexcom"; > + reg = <0xe0044000 0x100>; > + clocks = <&clks GCK_ID_FLEXCOM1>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0xe0044000 0x800>; > + status = "disabled"; > + }; > + > + trng: trng@e0048000 { Tudor already mentioned this.. > + compatible = "atmel,at91sam9g45-trng"; > + reg = <0xe0048000 0x100>; > + clocks = <&nic_clk>; > + }; > + > + aes: aes@e004c000 { .. and this .. > + compatible = "atmel,at91sam9g46-aes"; > + reg = <0xe004c000 0x100>; > + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&dma0 AT91_XDMAC_DT_PERID(13)>, > + <&dma0 AT91_XDMAC_DT_PERID(12)>; > + dma-names = "rx", "tx"; > + clocks = <&nic_clk>; > + clock-names = "aes_clk"; > + }; > + > + flx2: flexcom@e0060000 { > + compatible = "atmel,sama5d2-flexcom"; > + reg = <0xe0060000 0x100>; > + clocks = <&clks GCK_ID_FLEXCOM2>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0xe0060000 0x800>; > + status = "disabled"; > + }; > + > + flx3: flexcom@e0064000 { > + compatible = "atmel,sama5d2-flexcom"; > + reg = <0xe0064000 0x100>; > + clocks = <&clks GCK_ID_FLEXCOM3>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0xe0064000 0x800>; > + status = "disabled"; > + > + usart3: serial@200 { > + compatible = "atmel,at91sam9260-usart"; > + reg = <0x200 0x200>; > + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&nic_clk>; > + clock-names = "usart"; > + atmel,fifo-size = <32>; > + status = "disabled"; > + }; > + }; > + > + dma0: dma-controller@e0068000 { > + compatible = "microchip,sama7g5-dma"; > + reg = <0xe0068000 0x1000>; > + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; > + #dma-cells = <1>; > + clocks = <&nic_clk>; > + clock-names = "dma_clk"; > + }; > + > + sha: sha@e006c000 { .. and this one. > + compatible = "atmel,at91sam9g46-sha"; > + reg = <0xe006c000 0xec>; > + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>; > + dma-names = "tx"; > + clocks = <&nic_clk>; > + clock-names = "sha_clk"; > + }; > + > + flx4: flexcom@e0070000 { > + compatible = "atmel,sama5d2-flexcom"; > + reg = <0xe0070000 0x100>; > + clocks = <&clks GCK_ID_FLEXCOM4>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0xe0070000 0x800>; > + status = "disabled"; > + }; > + > + timer0: timer@e008c000 { > + compatible = "snps,dw-apb-timer"; > + reg = <0xe008c000 0x400>; > + clocks = <&nic_clk>; > + clock-names = "timer"; > + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + watchdog: watchdog@e0090000 { > + compatible = "snps,dw-wdt"; > + reg = <0xe0090000 0x1000>; > + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&nic_clk>; > + }; > + > + can0: can@e081c000 { > + compatible = "bosch,m_can"; > + reg = <0xe081c000 0xfc>, <0x00100000 0x4000>; > + reg-names = "m_can", "message_ram"; > + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "int0", "int1"; > + clocks = <&clks GCK_ID_MCAN0>, <&clks GCK_ID_MCAN0>; > + clock-names = "hclk", "cclk"; > + assigned-clocks = <&clks GCK_ID_MCAN0>; > + assigned-clock-rates = <40000000>; > + bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; > + status = "disabled"; > + }; > + > + gpio: pinctrl@e2004064 { > + compatible = "microchip,lan966x-pinctrl"; > + reg = <0xe2004064 0xb4>, > + <0xe2010024 0x138>; > + gpio-controller; > + #gpio-cells = <2>; > + gpio-ranges = <&gpio 0 0 78>; > + interrupt-controller; > + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; > + #interrupt-cells = <2>; > + }; > + > + gic: interrupt-controller@e8c11000 { > + compatible = "arm,gic-400", "arm,cortex-a7-gic"; > + #interrupt-cells = <3>; > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + reg = <0xe8c11000 0x1000>, > + <0xe8c12000 0x2000>, > + <0xe8c14000 0x2000>, > + <0xe8c16000 0x2000>; > + }; > + }; > +}; Overall most of the referenced bindings lack a proper yaml version :/ -michael
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > Hi, > > > arch/arm/boot/dts/Makefile | 2 + > > arch/arm/boot/dts/lan966x.dtsi | 237 ++++++++++++++++++++++++++ > > arch/arm/boot/dts/lan966x_pcb8291.dts | 61 +++++++ > > Please rename this to lan966x-pcb8921.dts. All (most?) of the device > tree files use the dash as a seperator between the SoC and the board. > Ok, I will change in my v6. Please have a look at my v5 patch where I already addressed all the node naming changes. > > diff --git a/arch/arm/boot/dts/lan966x.dtsi > b/arch/arm/boot/dts/lan966x.dtsi > > new file mode 100644 > > index 000000000000..91ee9e0684f4 > > --- /dev/null > > +++ b/arch/arm/boot/dts/lan966x.dtsi > > @@ -0,0 +1,237 @@ > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > +/* > > + * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC > > + * > > + * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries > > + * > > + * Author: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> > > + * > > + */ > > + > > +#include <dt-bindings/interrupt-controller/irq.h> > > +#include <dt-bindings/interrupt-controller/arm-gic.h> > > +#include <dt-bindings/mfd/atmel-flexcom.h> > > +#include <dt-bindings/dma/at91.h> > > +#include <dt-bindings/gpio/gpio.h> > > +#include <dt-bindings/clock/microchip,lan966x.h> > > + > > +/ { > > + model = "Microchip LAN966 family SoC"; > > + compatible = "microchip,lan966"; > > Undocumented compatible string. I see that the actual board > is documented in > Documentation/devicetree/bindings/arm/atmel-at91.yaml > > But as Arnd mentioned, this doesn't really make sense here > as you have to override it in the actual board dts anyway. > > > + interrupt-parent = <&gic>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + cpus { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + cpu@0 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a7"; > > + clock-frequency = <600000000>; > > + reg = <0x0>; > > + }; > > + }; > > + > > + clocks { > > + sys_clk: sys_clk { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <162500000>; > > + }; > > + > > + cpu_clk: cpu_clk { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <600000000>; > > + }; > > + > > + ddr_clk: ddr_clk { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <300000000>; > > + }; > > + > > + nic_clk: nic_clk { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <200000000>; > > + }; > > + }; > > + > > + clks: clock-controller@e00c00a8 { > > + compatible = "microchip,lan966x-gck"; > > + #clock-cells = <1>; > > + clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>; > > + clock-names = "cpu", "ddr", "sys"; > > + reg = <0xe00c00a8 0x38>; > > + }; > > + > > + timer { > > + compatible = "arm,armv7-timer"; > > + interrupt-parent = <&gic>; > > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | > IRQ_TYPE_LEVEL_LOW)>, > > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | > IRQ_TYPE_LEVEL_LOW)>, > > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | > IRQ_TYPE_LEVEL_LOW)>, > > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | > IRQ_TYPE_LEVEL_LOW)>; > > + clock-frequency = <37500000>; > > + arm,cpu-registers-not-fw-configured; > > + }; > > + > > + soc { > > + compatible = "simple-bus"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges; > > + > > + flx0: flexcom@e0040000 { > > + compatible = "atmel,sama5d2-flexcom"; > > Are these expected to be exactly the same between the lan966x and the > sama5d2 or do you need something like > > compatible = "microchip,lan966x-flexcom", "atmel,sama5d2-flexcom"; > > for the case when you need to make SoC specific settings/workarounds? > > > + reg = <0xe0040000 0x100>; > > + clocks = <&clks GCK_ID_FLEXCOM0>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges = <0x0 0xe0040000 0x800>; > > + status = "disabled"; > > + }; > > + > > + flx1: flexcom@e0044000 { > > + compatible = "atmel,sama5d2-flexcom"; > > + reg = <0xe0044000 0x100>; > > + clocks = <&clks GCK_ID_FLEXCOM1>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges = <0x0 0xe0044000 0x800>; > > + status = "disabled"; > > + }; > > + > > + trng: trng@e0048000 { > > Tudor already mentioned this.. > > > + compatible = "atmel,at91sam9g45-trng"; > > + reg = <0xe0048000 0x100>; > > + clocks = <&nic_clk>; > > + }; > > + > > + aes: aes@e004c000 { > > .. and this .. > > > + compatible = "atmel,at91sam9g46-aes"; > > + reg = <0xe004c000 0x100>; > > + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; > > + dmas = <&dma0 AT91_XDMAC_DT_PERID(13)>, > > + <&dma0 AT91_XDMAC_DT_PERID(12)>; > > + dma-names = "rx", "tx"; > > + clocks = <&nic_clk>; > > + clock-names = "aes_clk"; > > + }; > > + > > + flx2: flexcom@e0060000 { > > + compatible = "atmel,sama5d2-flexcom"; > > + reg = <0xe0060000 0x100>; > > + clocks = <&clks GCK_ID_FLEXCOM2>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges = <0x0 0xe0060000 0x800>; > > + status = "disabled"; > > + }; > > + > > + flx3: flexcom@e0064000 { > > + compatible = "atmel,sama5d2-flexcom"; > > + reg = <0xe0064000 0x100>; > > + clocks = <&clks GCK_ID_FLEXCOM3>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges = <0x0 0xe0064000 0x800>; > > + status = "disabled"; > > + > > + usart3: serial@200 { > > + compatible = "atmel,at91sam9260-usart"; > > + reg = <0x200 0x200>; > > + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&nic_clk>; > > + clock-names = "usart"; > > + atmel,fifo-size = <32>; > > + status = "disabled"; > > + }; > > + }; > > + > > + dma0: dma-controller@e0068000 { > > + compatible = "microchip,sama7g5-dma"; > > + reg = <0xe0068000 0x1000>; > > + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; > > + #dma-cells = <1>; > > + clocks = <&nic_clk>; > > + clock-names = "dma_clk"; > > + }; > > + > > + sha: sha@e006c000 { > > .. and this one. > > > + compatible = "atmel,at91sam9g46-sha"; > > + reg = <0xe006c000 0xec>; > > + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; > > + dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>; > > + dma-names = "tx"; > > + clocks = <&nic_clk>; > > + clock-names = "sha_clk"; > > + }; > > + > > + flx4: flexcom@e0070000 { > > + compatible = "atmel,sama5d2-flexcom"; > > + reg = <0xe0070000 0x100>; > > + clocks = <&clks GCK_ID_FLEXCOM4>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges = <0x0 0xe0070000 0x800>; > > + status = "disabled"; > > + }; > > + > > + timer0: timer@e008c000 { > > + compatible = "snps,dw-apb-timer"; > > + reg = <0xe008c000 0x400>; > > + clocks = <&nic_clk>; > > + clock-names = "timer"; > > + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + > > + watchdog: watchdog@e0090000 { > > + compatible = "snps,dw-wdt"; > > + reg = <0xe0090000 0x1000>; > > + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&nic_clk>; > > + }; > > + > > + can0: can@e081c000 { > > + compatible = "bosch,m_can"; > > + reg = <0xe081c000 0xfc>, <0x00100000 0x4000>; > > + reg-names = "m_can", "message_ram"; > > + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-names = "int0", "int1"; > > + clocks = <&clks GCK_ID_MCAN0>, <&clks GCK_ID_MCAN0>; > > + clock-names = "hclk", "cclk"; > > + assigned-clocks = <&clks GCK_ID_MCAN0>; > > + assigned-clock-rates = <40000000>; > > + bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; > > + status = "disabled"; > > + }; > > + > > + gpio: pinctrl@e2004064 { > > + compatible = "microchip,lan966x-pinctrl"; > > + reg = <0xe2004064 0xb4>, > > + <0xe2010024 0x138>; > > + gpio-controller; > > + #gpio-cells = <2>; > > + gpio-ranges = <&gpio 0 0 78>; > > + interrupt-controller; > > + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; > > + #interrupt-cells = <2>; > > + }; > > + > > + gic: interrupt-controller@e8c11000 { > > + compatible = "arm,gic-400", "arm,cortex-a7-gic"; > > + #interrupt-cells = <3>; > > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-controller; > > + reg = <0xe8c11000 0x1000>, > > + <0xe8c12000 0x2000>, > > + <0xe8c14000 0x2000>, > > + <0xe8c16000 0x2000>; > > + }; > > + }; > > +}; > > Overall most of the referenced bindings lack a proper yaml version :/ > > -michael
Am 2022-02-10 14:02, schrieb Kavyasree.Kotagiri@microchip.com: >> EXTERNAL EMAIL: Do not click links or open attachments unless you know >> the >> content is safe >> >> Hi, >> >> > arch/arm/boot/dts/Makefile | 2 + >> > arch/arm/boot/dts/lan966x.dtsi | 237 ++++++++++++++++++++++++++ >> > arch/arm/boot/dts/lan966x_pcb8291.dts | 61 +++++++ >> >> Please rename this to lan966x-pcb8921.dts. All (most?) of the device >> tree files use the dash as a seperator between the SoC and the board. >> > Ok, I will change in my v6. > Please have a look at my v5 patch where I already addressed all the > node naming changes. My comments besides the renaming still apply. -michael
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > Hi, > > > arch/arm/boot/dts/Makefile | 2 + > > arch/arm/boot/dts/lan966x.dtsi | 237 ++++++++++++++++++++++++++ > > arch/arm/boot/dts/lan966x_pcb8291.dts | 61 +++++++ > > Please rename this to lan966x-pcb8921.dts. All (most?) of the device > tree files use the dash as a seperator between the SoC and the board. > Ok. I will change it. > > diff --git a/arch/arm/boot/dts/lan966x.dtsi > b/arch/arm/boot/dts/lan966x.dtsi > > new file mode 100644 > > index 000000000000..91ee9e0684f4 > > --- /dev/null > > +++ b/arch/arm/boot/dts/lan966x.dtsi > > @@ -0,0 +1,237 @@ > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > +/* > > + * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC > > + * > > + * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries > > + * > > + * Author: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> > > + * > > + */ > > + > > +#include <dt-bindings/interrupt-controller/irq.h> > > +#include <dt-bindings/interrupt-controller/arm-gic.h> > > +#include <dt-bindings/mfd/atmel-flexcom.h> > > +#include <dt-bindings/dma/at91.h> > > +#include <dt-bindings/gpio/gpio.h> > > +#include <dt-bindings/clock/microchip,lan966x.h> > > + > > +/ { > > + model = "Microchip LAN966 family SoC"; > > + compatible = "microchip,lan966"; > > Undocumented compatible string. I see that the actual board > is documented in > Documentation/devicetree/bindings/arm/atmel-at91.yaml > > But as Arnd mentioned, this doesn't really make sense here > as you have to override it in the actual board dts anyway. > > > + interrupt-parent = <&gic>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + cpus { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + cpu@0 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a7"; > > + clock-frequency = <600000000>; > > + reg = <0x0>; > > + }; > > + }; > > + > > + clocks { > > + sys_clk: sys_clk { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <162500000>; > > + }; > > + > > + cpu_clk: cpu_clk { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <600000000>; > > + }; > > + > > + ddr_clk: ddr_clk { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <300000000>; > > + }; > > + > > + nic_clk: nic_clk { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <200000000>; > > + }; > > + }; > > + > > + clks: clock-controller@e00c00a8 { > > + compatible = "microchip,lan966x-gck"; > > + #clock-cells = <1>; > > + clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>; > > + clock-names = "cpu", "ddr", "sys"; > > + reg = <0xe00c00a8 0x38>; > > + }; > > + > > + timer { > > + compatible = "arm,armv7-timer"; > > + interrupt-parent = <&gic>; > > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | > IRQ_TYPE_LEVEL_LOW)>, > > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | > IRQ_TYPE_LEVEL_LOW)>, > > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | > IRQ_TYPE_LEVEL_LOW)>, > > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | > IRQ_TYPE_LEVEL_LOW)>; > > + clock-frequency = <37500000>; > > + arm,cpu-registers-not-fw-configured; > > + }; > > + > > + soc { > > + compatible = "simple-bus"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges; > > + > > + flx0: flexcom@e0040000 { > > + compatible = "atmel,sama5d2-flexcom"; > > Are these expected to be exactly the same between the lan966x and the > sama5d2 or do you need something like > > compatible = "microchip,lan966x-flexcom", "atmel,sama5d2-flexcom"; > > for the case when you need to make SoC specific settings/workarounds? > Yes, it is the same. No workarounds required. > > + reg = <0xe0040000 0x100>; > > + clocks = <&clks GCK_ID_FLEXCOM0>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges = <0x0 0xe0040000 0x800>; > > + status = "disabled"; > > + }; > > + > > + flx1: flexcom@e0044000 { > > + compatible = "atmel,sama5d2-flexcom"; > > + reg = <0xe0044000 0x100>; > > + clocks = <&clks GCK_ID_FLEXCOM1>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges = <0x0 0xe0044000 0x800>; > > + status = "disabled"; > > + }; > > + > > + trng: trng@e0048000 { > > Tudor already mentioned this.. > > > + compatible = "atmel,at91sam9g45-trng"; > > + reg = <0xe0048000 0x100>; > > + clocks = <&nic_clk>; > > + }; > > + > > + aes: aes@e004c000 { > > .. and this .. > > > + compatible = "atmel,at91sam9g46-aes"; > > + reg = <0xe004c000 0x100>; > > + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; > > + dmas = <&dma0 AT91_XDMAC_DT_PERID(13)>, > > + <&dma0 AT91_XDMAC_DT_PERID(12)>; > > + dma-names = "rx", "tx"; > > + clocks = <&nic_clk>; > > + clock-names = "aes_clk"; > > + }; > > + > > + flx2: flexcom@e0060000 { > > + compatible = "atmel,sama5d2-flexcom"; > > + reg = <0xe0060000 0x100>; > > + clocks = <&clks GCK_ID_FLEXCOM2>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges = <0x0 0xe0060000 0x800>; > > + status = "disabled"; > > + }; > > + > > + flx3: flexcom@e0064000 { > > + compatible = "atmel,sama5d2-flexcom"; > > + reg = <0xe0064000 0x100>; > > + clocks = <&clks GCK_ID_FLEXCOM3>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges = <0x0 0xe0064000 0x800>; > > + status = "disabled"; > > + > > + usart3: serial@200 { > > + compatible = "atmel,at91sam9260-usart"; > > + reg = <0x200 0x200>; > > + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&nic_clk>; > > + clock-names = "usart"; > > + atmel,fifo-size = <32>; > > + status = "disabled"; > > + }; > > + }; > > + > > + dma0: dma-controller@e0068000 { > > + compatible = "microchip,sama7g5-dma"; > > + reg = <0xe0068000 0x1000>; > > + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; > > + #dma-cells = <1>; > > + clocks = <&nic_clk>; > > + clock-names = "dma_clk"; > > + }; > > + > > + sha: sha@e006c000 { > > .. and this one. > > > + compatible = "atmel,at91sam9g46-sha"; > > + reg = <0xe006c000 0xec>; > > + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; > > + dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>; > > + dma-names = "tx"; > > + clocks = <&nic_clk>; > > + clock-names = "sha_clk"; > > + }; > > + > > + flx4: flexcom@e0070000 { > > + compatible = "atmel,sama5d2-flexcom"; > > + reg = <0xe0070000 0x100>; > > + clocks = <&clks GCK_ID_FLEXCOM4>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges = <0x0 0xe0070000 0x800>; > > + status = "disabled"; > > + }; > > + > > + timer0: timer@e008c000 { > > + compatible = "snps,dw-apb-timer"; > > + reg = <0xe008c000 0x400>; > > + clocks = <&nic_clk>; > > + clock-names = "timer"; > > + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + > > + watchdog: watchdog@e0090000 { > > + compatible = "snps,dw-wdt"; > > + reg = <0xe0090000 0x1000>; > > + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&nic_clk>; > > + }; > > + > > + can0: can@e081c000 { > > + compatible = "bosch,m_can"; > > + reg = <0xe081c000 0xfc>, <0x00100000 0x4000>; > > + reg-names = "m_can", "message_ram"; > > + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-names = "int0", "int1"; > > + clocks = <&clks GCK_ID_MCAN0>, <&clks GCK_ID_MCAN0>; > > + clock-names = "hclk", "cclk"; > > + assigned-clocks = <&clks GCK_ID_MCAN0>; > > + assigned-clock-rates = <40000000>; > > + bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; > > + status = "disabled"; > > + }; > > + > > + gpio: pinctrl@e2004064 { > > + compatible = "microchip,lan966x-pinctrl"; > > + reg = <0xe2004064 0xb4>, > > + <0xe2010024 0x138>; > > + gpio-controller; > > + #gpio-cells = <2>; > > + gpio-ranges = <&gpio 0 0 78>; > > + interrupt-controller; > > + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; > > + #interrupt-cells = <2>; > > + }; > > + > > + gic: interrupt-controller@e8c11000 { > > + compatible = "arm,gic-400", "arm,cortex-a7-gic"; > > + #interrupt-cells = <3>; > > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-controller; > > + reg = <0xe8c11000 0x1000>, > > + <0xe8c12000 0x2000>, > > + <0xe8c14000 0x2000>, > > + <0xe8c16000 0x2000>; > > + }; > > + }; > > +}; > > Overall most of the referenced bindings lack a proper yaml version :/ > > -michael
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > Am 2022-02-10 12:52, schrieb Kavyasree.Kotagiri@microchip.com: > >> EXTERNAL EMAIL: Do not click links or open attachments unless you know > >> the > >> content is safe > >> > >> Am 2022-02-10 10:40, schrieb Kavyasree.Kotagiri@microchip.com: > >> >> EXTERNAL EMAIL: Do not click links or open attachments unless you > know > >> >> the > >> >> content is safe > >> > >> >> > + clocks { > >> >> [..] > >> >> > + > >> >> > + nic_clk: nic_clk { > >> >> > >> >> What does nic_clk stand for? If I had to guess, it > >> >> has something to do with network. But.. > >> >> > >> > NIC clock is the clock used by AXI, AHB fabric and APB bridges which > >> > connects all the peripherals. > >> > It is named so because the AXI fabric is based on NIC400 IP from ARM > >> > >> Ok, thanks for clarification. > >> > >> > >> >> > + watchdog: watchdog@e0090000 { > >> >> > + compatible = "snps,dw-wdt"; > >> >> > + reg = <0xe0090000 0x1000>; > >> >> > + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; > >> >> > + clocks = <&nic_clk>; > >> >> > >> >> Btw. can we disable all nodes by default and enable them > >> >> in the board dts files? > >> > I would like to have only board specific nodes enabled in dts files > >> > and rest of them in dtsi file > >> > >> And how do you know which ones are board specific? E.g. I would like > >> to add our board which is also based on the lan9668. Maybe I don't > >> want a watchdog (or whatever node). Of course I could use > >> > >> &watchdog { > >> status = "disabled"; > >> }; > >> > >> But IMHO opt-in is better. At least thats what we are doing for > >> the layerscape over on arm64. > >> > > Basically, I am disabling only the nodes which have pinctrl settings > > in dtsi file > > and enable in dts to make sure there are no conflicts on pins on the > > board. > > Thats not what I'm asking. I would like to see *optional* nodes > disabled by default. Whether the watchdog is optional might be > debatable, but what about the usb controller and the qspi > controller? They don't have shared pins AFAIK, so according > to your rule, they will be enabled by default and each board > which doesn't have anything connected on these pins would have > to disabled it. > > Please keep in mind that this .dtsi will also be used by boards > not manufactured by microchip. > I agree with you - "disabling optional nodes in dtsi" I have gone through all the nodes. Confirmed and moved enabling optional node watchdog to dts file. > -michael
Am 2022-02-18 13:28, schrieb Kavyasree.Kotagiri@microchip.com: >> EXTERNAL EMAIL: Do not click links or open attachments unless you know >> the >> content is safe >> >> Am 2022-02-10 12:52, schrieb Kavyasree.Kotagiri@microchip.com: >> >> EXTERNAL EMAIL: Do not click links or open attachments unless you know >> >> the >> >> content is safe >> >> >> >> Am 2022-02-10 10:40, schrieb Kavyasree.Kotagiri@microchip.com: >> >> >> EXTERNAL EMAIL: Do not click links or open attachments unless you >> know >> >> >> the >> >> >> content is safe >> >> >> >> >> > + clocks { >> >> >> [..] >> >> >> > + >> >> >> > + nic_clk: nic_clk { >> >> >> >> >> >> What does nic_clk stand for? If I had to guess, it >> >> >> has something to do with network. But.. >> >> >> >> >> > NIC clock is the clock used by AXI, AHB fabric and APB bridges which >> >> > connects all the peripherals. >> >> > It is named so because the AXI fabric is based on NIC400 IP from ARM >> >> >> >> Ok, thanks for clarification. >> >> >> >> >> >> >> > + watchdog: watchdog@e0090000 { >> >> >> > + compatible = "snps,dw-wdt"; >> >> >> > + reg = <0xe0090000 0x1000>; >> >> >> > + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; >> >> >> > + clocks = <&nic_clk>; >> >> >> >> >> >> Btw. can we disable all nodes by default and enable them >> >> >> in the board dts files? >> >> > I would like to have only board specific nodes enabled in dts files >> >> > and rest of them in dtsi file >> >> >> >> And how do you know which ones are board specific? E.g. I would like >> >> to add our board which is also based on the lan9668. Maybe I don't >> >> want a watchdog (or whatever node). Of course I could use >> >> >> >> &watchdog { >> >> status = "disabled"; >> >> }; >> >> >> >> But IMHO opt-in is better. At least thats what we are doing for >> >> the layerscape over on arm64. >> >> >> > Basically, I am disabling only the nodes which have pinctrl settings >> > in dtsi file >> > and enable in dts to make sure there are no conflicts on pins on the >> > board. >> >> Thats not what I'm asking. I would like to see *optional* nodes >> disabled by default. Whether the watchdog is optional might be >> debatable, but what about the usb controller and the qspi >> controller? They don't have shared pins AFAIK, so according >> to your rule, they will be enabled by default and each board >> which doesn't have anything connected on these pins would have >> to disabled it. >> >> Please keep in mind that this .dtsi will also be used by boards >> not manufactured by microchip. >> > I agree with you - "disabling optional nodes in dtsi" > I have gone through all the nodes. > Confirmed and moved enabling optional node watchdog > to dts file. Great, I just wanted to get to an agreement how the optional nodes should be handled. If it turns out, some are still optional or some aren't. It is easy to just mark them disabled and enable them in the board dts files in a later patch. -michael
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > Am 2022-02-18 13:28, schrieb Kavyasree.Kotagiri@microchip.com: > >> EXTERNAL EMAIL: Do not click links or open attachments unless you know > >> the > >> content is safe > >> > >> Am 2022-02-10 12:52, schrieb Kavyasree.Kotagiri@microchip.com: > >> >> EXTERNAL EMAIL: Do not click links or open attachments unless you > know > >> >> the > >> >> content is safe > >> >> > >> >> Am 2022-02-10 10:40, schrieb Kavyasree.Kotagiri@microchip.com: > >> >> >> EXTERNAL EMAIL: Do not click links or open attachments unless you > >> know > >> >> >> the > >> >> >> content is safe > >> >> > >> >> >> > + clocks { > >> >> >> [..] > >> >> >> > + > >> >> >> > + nic_clk: nic_clk { > >> >> >> > >> >> >> What does nic_clk stand for? If I had to guess, it > >> >> >> has something to do with network. But.. > >> >> >> > >> >> > NIC clock is the clock used by AXI, AHB fabric and APB bridges which > >> >> > connects all the peripherals. > >> >> > It is named so because the AXI fabric is based on NIC400 IP from ARM > >> >> > >> >> Ok, thanks for clarification. > >> >> > >> >> > >> >> >> > + watchdog: watchdog@e0090000 { > >> >> >> > + compatible = "snps,dw-wdt"; > >> >> >> > + reg = <0xe0090000 0x1000>; > >> >> >> > + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; > >> >> >> > + clocks = <&nic_clk>; > >> >> >> > >> >> >> Btw. can we disable all nodes by default and enable them > >> >> >> in the board dts files? > >> >> > I would like to have only board specific nodes enabled in dts files > >> >> > and rest of them in dtsi file > >> >> > >> >> And how do you know which ones are board specific? E.g. I would like > >> >> to add our board which is also based on the lan9668. Maybe I don't > >> >> want a watchdog (or whatever node). Of course I could use > >> >> > >> >> &watchdog { > >> >> status = "disabled"; > >> >> }; > >> >> > >> >> But IMHO opt-in is better. At least thats what we are doing for > >> >> the layerscape over on arm64. > >> >> > >> > Basically, I am disabling only the nodes which have pinctrl settings > >> > in dtsi file > >> > and enable in dts to make sure there are no conflicts on pins on the > >> > board. > >> > >> Thats not what I'm asking. I would like to see *optional* nodes > >> disabled by default. Whether the watchdog is optional might be > >> debatable, but what about the usb controller and the qspi > >> controller? They don't have shared pins AFAIK, so according > >> to your rule, they will be enabled by default and each board > >> which doesn't have anything connected on these pins would have > >> to disabled it. > >> > >> Please keep in mind that this .dtsi will also be used by boards > >> not manufactured by microchip. > >> > > I agree with you - "disabling optional nodes in dtsi" > > I have gone through all the nodes. > > Confirmed and moved enabling optional node watchdog > > to dts file. > > Great, I just wanted to get to an agreement how the optional nodes > should be handled. If it turns out, some are still optional or > some aren't. It is easy to just mark them disabled and enable them > in the board dts files in a later patch. > Sorry, I didn't get you. Do you still see optional nodes in my dtsi? I think GPIO controller, Interrupt controller, XDMA, timers, AES, SHA, TRNG are not optional. So, I keep them enabled in dtsi. Please let me know your comments. > -michael
Am 2022-02-21 06:44, schrieb Kavyasree.Kotagiri@microchip.com: >> EXTERNAL EMAIL: Do not click links or open attachments unless you know >> the >> content is safe >> >> Am 2022-02-18 13:28, schrieb Kavyasree.Kotagiri@microchip.com: >> >> EXTERNAL EMAIL: Do not click links or open attachments unless you know >> >> the >> >> content is safe >> >> >> >> Am 2022-02-10 12:52, schrieb Kavyasree.Kotagiri@microchip.com: >> >> >> EXTERNAL EMAIL: Do not click links or open attachments unless you >> know >> >> >> the >> >> >> content is safe >> >> >> >> >> >> Am 2022-02-10 10:40, schrieb Kavyasree.Kotagiri@microchip.com: >> >> >> >> EXTERNAL EMAIL: Do not click links or open attachments unless you >> >> know >> >> >> >> the >> >> >> >> content is safe >> >> >> >> >> >> >> > + clocks { >> >> >> >> [..] >> >> >> >> > + >> >> >> >> > + nic_clk: nic_clk { >> >> >> >> >> >> >> >> What does nic_clk stand for? If I had to guess, it >> >> >> >> has something to do with network. But.. >> >> >> >> >> >> >> > NIC clock is the clock used by AXI, AHB fabric and APB bridges which >> >> >> > connects all the peripherals. >> >> >> > It is named so because the AXI fabric is based on NIC400 IP from ARM >> >> >> >> >> >> Ok, thanks for clarification. >> >> >> >> >> >> >> >> >> >> > + watchdog: watchdog@e0090000 { >> >> >> >> > + compatible = "snps,dw-wdt"; >> >> >> >> > + reg = <0xe0090000 0x1000>; >> >> >> >> > + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; >> >> >> >> > + clocks = <&nic_clk>; >> >> >> >> >> >> >> >> Btw. can we disable all nodes by default and enable them >> >> >> >> in the board dts files? >> >> >> > I would like to have only board specific nodes enabled in dts files >> >> >> > and rest of them in dtsi file >> >> >> >> >> >> And how do you know which ones are board specific? E.g. I would like >> >> >> to add our board which is also based on the lan9668. Maybe I don't >> >> >> want a watchdog (or whatever node). Of course I could use >> >> >> >> >> >> &watchdog { >> >> >> status = "disabled"; >> >> >> }; >> >> >> >> >> >> But IMHO opt-in is better. At least thats what we are doing for >> >> >> the layerscape over on arm64. >> >> >> >> >> > Basically, I am disabling only the nodes which have pinctrl settings >> >> > in dtsi file >> >> > and enable in dts to make sure there are no conflicts on pins on the >> >> > board. >> >> >> >> Thats not what I'm asking. I would like to see *optional* nodes >> >> disabled by default. Whether the watchdog is optional might be >> >> debatable, but what about the usb controller and the qspi >> >> controller? They don't have shared pins AFAIK, so according >> >> to your rule, they will be enabled by default and each board >> >> which doesn't have anything connected on these pins would have >> >> to disabled it. >> >> >> >> Please keep in mind that this .dtsi will also be used by boards >> >> not manufactured by microchip. >> >> >> > I agree with you - "disabling optional nodes in dtsi" >> > I have gone through all the nodes. >> > Confirmed and moved enabling optional node watchdog >> > to dts file. >> >> Great, I just wanted to get to an agreement how the optional nodes >> should be handled. If it turns out, some are still optional or >> some aren't. It is easy to just mark them disabled and enable them >> in the board dts files in a later patch. >> > Sorry, I didn't get you. Do you still see optional nodes in my dtsi? > I think GPIO controller, Interrupt controller, XDMA, timers, AES, SHA, > TRNG are > not optional. So, I keep them enabled in dtsi. Agreed. Once you posted a new version, I'll post an RFC (or a regular patch depending how fast this is picked up) for our board based on the LAN966x. -michael
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 235ad559acb2..2040a990f08c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -735,6 +735,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \ dtb-$(CONFIG_SOC_IMX7ULP) += \ imx7ulp-com.dtb \ imx7ulp-evk.dtb +dtb-$(CONFIG_SOC_LAN966) += \ + lan966x_pcb8291.dtb dtb-$(CONFIG_SOC_LS1021A) += \ ls1021a-moxa-uc-8410a.dtb \ ls1021a-qds.dtb \ diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi new file mode 100644 index 000000000000..91ee9e0684f4 --- /dev/null +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC + * + * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries + * + * Author: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> + * + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/mfd/atmel-flexcom.h> +#include <dt-bindings/dma/at91.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/microchip,lan966x.h> + +/ { + model = "Microchip LAN966 family SoC"; + compatible = "microchip,lan966"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + clock-frequency = <600000000>; + reg = <0x0>; + }; + }; + + clocks { + sys_clk: sys_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <162500000>; + }; + + cpu_clk: cpu_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <600000000>; + }; + + ddr_clk: ddr_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <300000000>; + }; + + nic_clk: nic_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + }; + + clks: clock-controller@e00c00a8 { + compatible = "microchip,lan966x-gck"; + #clock-cells = <1>; + clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>; + clock-names = "cpu", "ddr", "sys"; + reg = <0xe00c00a8 0x38>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <37500000>; + arm,cpu-registers-not-fw-configured; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + flx0: flexcom@e0040000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe0040000 0x100>; + clocks = <&clks GCK_ID_FLEXCOM0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0040000 0x800>; + status = "disabled"; + }; + + flx1: flexcom@e0044000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe0044000 0x100>; + clocks = <&clks GCK_ID_FLEXCOM1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0044000 0x800>; + status = "disabled"; + }; + + trng: trng@e0048000 { + compatible = "atmel,at91sam9g45-trng"; + reg = <0xe0048000 0x100>; + clocks = <&nic_clk>; + }; + + aes: aes@e004c000 { + compatible = "atmel,at91sam9g46-aes"; + reg = <0xe004c000 0x100>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(13)>, + <&dma0 AT91_XDMAC_DT_PERID(12)>; + dma-names = "rx", "tx"; + clocks = <&nic_clk>; + clock-names = "aes_clk"; + }; + + flx2: flexcom@e0060000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe0060000 0x100>; + clocks = <&clks GCK_ID_FLEXCOM2>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0060000 0x800>; + status = "disabled"; + }; + + flx3: flexcom@e0064000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe0064000 0x100>; + clocks = <&clks GCK_ID_FLEXCOM3>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0064000 0x800>; + status = "disabled"; + + usart3: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&nic_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + }; + + dma0: dma-controller@e0068000 { + compatible = "microchip,sama7g5-dma"; + reg = <0xe0068000 0x1000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&nic_clk>; + clock-names = "dma_clk"; + }; + + sha: sha@e006c000 { + compatible = "atmel,at91sam9g46-sha"; + reg = <0xe006c000 0xec>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>; + dma-names = "tx"; + clocks = <&nic_clk>; + clock-names = "sha_clk"; + }; + + flx4: flexcom@e0070000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe0070000 0x100>; + clocks = <&clks GCK_ID_FLEXCOM4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0070000 0x800>; + status = "disabled"; + }; + + timer0: timer@e008c000 { + compatible = "snps,dw-apb-timer"; + reg = <0xe008c000 0x400>; + clocks = <&nic_clk>; + clock-names = "timer"; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + }; + + watchdog: watchdog@e0090000 { + compatible = "snps,dw-wdt"; + reg = <0xe0090000 0x1000>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&nic_clk>; + }; + + can0: can@e081c000 { + compatible = "bosch,m_can"; + reg = <0xe081c000 0xfc>, <0x00100000 0x4000>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + clocks = <&clks GCK_ID_MCAN0>, <&clks GCK_ID_MCAN0>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&clks GCK_ID_MCAN0>; + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + gpio: pinctrl@e2004064 { + compatible = "microchip,lan966x-pinctrl"; + reg = <0xe2004064 0xb4>, + <0xe2010024 0x138>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 78>; + interrupt-controller; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + }; + + gic: interrupt-controller@e8c11000 { + compatible = "arm,gic-400", "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + reg = <0xe8c11000 0x1000>, + <0xe8c12000 0x2000>, + <0xe8c14000 0x2000>, + <0xe8c16000 0x2000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/lan966x_pcb8291.dts b/arch/arm/boot/dts/lan966x_pcb8291.dts new file mode 100644 index 000000000000..ccec4177990b --- /dev/null +++ b/arch/arm/boot/dts/lan966x_pcb8291.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * lan966x_pcb8291.dts - Device Tree file for PCB8291 + */ +/dts-v1/; +#include "lan966x.dtsi" + +/ { + model = "Microchip EVB - LAN9662"; + compatible = "microchip,lan9662-pcb8291", "microchip,lan9662", "microchip,lan966"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &usart3; + }; +}; + +&gpio { + fc_shrd7_pins: fc_shrd7-pins { + pins = "GPIO_49"; + function = "fc_shrd7"; + }; + + fc_shrd8_pins: fc_shrd8-pins { + pins = "GPIO_54"; + function = "fc_shrd8"; + }; + + fc3_b_pins: fcb3-spi-pins { + /* SCK, RXD, TXD */ + pins = "GPIO_51", "GPIO_52", "GPIO_53"; + function = "fc3_b"; + }; + + can0_b_pins: can0_b_pins { + /* RX, TX */ + pins = "GPIO_35", "GPIO_36"; + function = "can0_b"; + }; +}; + +&can0 { + pinctrl-0 = <&can0_b_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&flx3 { + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>; + status = "okay"; + + usart3: serial@200 { + pinctrl-0 = <&fc3_b_pins>, <&fc_shrd7_pins>, <&fc_shrd8_pins>; + pinctrl-names = "default"; + status = "okay"; + }; +}; +
This patch adds basic DT for Microchip lan966x SoC and associated board pcb8291(2-port EVB). Adds peripherals required to allow booting: Interrupt Controller, Clock, Generic ARMv7 Timers, Synopsys Timer, Flexcoms, GPIOs. Also adds other peripherals like crypto(AES/SHA), DMA, Watchdog Timer, TRNG and MCAN0. Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> --- v3 -> v4: - Removed character 'x' from compatible string. - Removed memory node as handled by bootloader. - Renamed flexcom3 usart0 to usart3 - Added /chosen and /aliases nodes in dts file. v2 -> v3: - Enabling trng in dtsi itself. - Removed "status=okay" dma0. - Add gpio pin settings for can0(missed adding this in previous version) v1 -> v2: - Moved flx3 usart0 node to dtsi file. - Removed status="okay" for dma0 to maintain consistency across nodes (which means enabling dma0 by default) arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/lan966x.dtsi | 237 ++++++++++++++++++++++++++ arch/arm/boot/dts/lan966x_pcb8291.dts | 61 +++++++ 3 files changed, 300 insertions(+) create mode 100644 arch/arm/boot/dts/lan966x.dtsi create mode 100644 arch/arm/boot/dts/lan966x_pcb8291.dts