| Message ID | 1645420953-21176-3-git-send-email-quic_rohiagar@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add APCS support for SDX65 | expand |
On Mon, Feb 21, 2022 at 10:52:28AM +0530, Rohit Agarwal wrote: > In SDX65, the IPC bits are located in the APCS GCC block. Also, this block > can provide clock functionality. Hence, add support for IPC with correct > offset and name of the clock provider. > > Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> > --- > drivers/mailbox/qcom-apcs-ipc-mailbox.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c > index 9325d2a..54d7659 100644 > --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c > +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c > @@ -53,6 +53,10 @@ static const struct qcom_apcs_ipc_data sdx55_apcs_data = { > .offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk" > }; > > +static const struct qcom_apcs_ipc_data sdx65_apcs_data = { > + .offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk" > +}; What I suggested was reusing the "qcom,sdx55-apcs-gcc" compatible in devicetree. So with that, you won't need this specific compatible for SDX65 that essentially duplicates SDX55. Thanks, Mani > + > static const struct regmap_config apcs_regmap_config = { > .reg_bits = 32, > .reg_stride = 4, > @@ -159,6 +163,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = { > { .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data }, > { .compatible = "qcom,sm6115-apcs-hmss-global", .data = &msm8994_apcs_data }, > { .compatible = "qcom,sdx55-apcs-gcc", .data = &sdx55_apcs_data }, > + { .compatible = "qcom,sdx65-apcs-gcc", .data = &sdx65_apcs_data }, > {} > }; > MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match); > -- > 2.7.4 >
On 2/21/2022 11:05 AM, Manivannan Sadhasivam wrote: > On Mon, Feb 21, 2022 at 10:52:28AM +0530, Rohit Agarwal wrote: >> In SDX65, the IPC bits are located in the APCS GCC block. Also, this block >> can provide clock functionality. Hence, add support for IPC with correct >> offset and name of the clock provider. >> >> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> >> --- >> drivers/mailbox/qcom-apcs-ipc-mailbox.c | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c >> index 9325d2a..54d7659 100644 >> --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c >> +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c >> @@ -53,6 +53,10 @@ static const struct qcom_apcs_ipc_data sdx55_apcs_data = { >> .offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk" >> }; >> >> +static const struct qcom_apcs_ipc_data sdx65_apcs_data = { >> + .offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk" >> +}; > What I suggested was reusing the "qcom,sdx55-apcs-gcc" compatible in devicetree. > So with that, you won't need this specific compatible for SDX65 that essentially > duplicates SDX55. Clear. Will update. Thanks! > Thanks, > Mani > >> + >> static const struct regmap_config apcs_regmap_config = { >> .reg_bits = 32, >> .reg_stride = 4, >> @@ -159,6 +163,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = { >> { .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data }, >> { .compatible = "qcom,sm6115-apcs-hmss-global", .data = &msm8994_apcs_data }, >> { .compatible = "qcom,sdx55-apcs-gcc", .data = &sdx55_apcs_data }, >> + { .compatible = "qcom,sdx65-apcs-gcc", .data = &sdx65_apcs_data }, >> {} >> }; >> MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match); >> -- >> 2.7.4 >>
diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c index 9325d2a..54d7659 100644 --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c @@ -53,6 +53,10 @@ static const struct qcom_apcs_ipc_data sdx55_apcs_data = { .offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk" }; +static const struct qcom_apcs_ipc_data sdx65_apcs_data = { + .offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk" +}; + static const struct regmap_config apcs_regmap_config = { .reg_bits = 32, .reg_stride = 4, @@ -159,6 +163,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = { { .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data }, { .compatible = "qcom,sm6115-apcs-hmss-global", .data = &msm8994_apcs_data }, { .compatible = "qcom,sdx55-apcs-gcc", .data = &sdx55_apcs_data }, + { .compatible = "qcom,sdx65-apcs-gcc", .data = &sdx65_apcs_data }, {} }; MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);
In SDX65, the IPC bits are located in the APCS GCC block. Also, this block can provide clock functionality. Hence, add support for IPC with correct offset and name of the clock provider. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 5 +++++ 1 file changed, 5 insertions(+)