Message ID | 20220223064358.4097307-5-peng.fan@oss.nxp.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | imx: add i.MX93 clk bindings and driver | expand |
On 22-02-23 14:43:57, Peng Fan (OSS) wrote: > From: Peng Fan <peng.fan@nxp.com> > > This PLL module is a Fractional-N synthesizer, > supporting 30-bit numerator and denominator. Numerator is a signed > number. It has feature to adjust fractional portion of feedback > divider dynamically. This fracn gppll is used in i.MX93. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- > drivers/clk/imx/Makefile | 1 + > drivers/clk/imx/clk-fracn-gppll.c | 328 ++++++++++++++++++++++++++++++ > drivers/clk/imx/clk.h | 21 ++ > 3 files changed, 350 insertions(+) > create mode 100644 drivers/clk/imx/clk-fracn-gppll.c > > diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile > index 36c04922d789..60c8a4bb7574 100644 > --- a/drivers/clk/imx/Makefile > +++ b/drivers/clk/imx/Makefile > @@ -5,6 +5,7 @@ mxc-clk-objs += clk-busy.o > mxc-clk-objs += clk-composite-7ulp.o > mxc-clk-objs += clk-composite-8m.o > mxc-clk-objs += clk-composite-93.o > +mxc-clk-objs += clk-fracn-gppll.o > mxc-clk-objs += clk-cpu.o > mxc-clk-objs += clk-divider-gate.o > mxc-clk-objs += clk-fixup-div.o > diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c > new file mode 100644 > index 000000000000..6c9946a4bdb7 > --- /dev/null > +++ b/drivers/clk/imx/clk-fracn-gppll.c > @@ -0,0 +1,328 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright 2021 NXP > + */ > + > +#include <linux/bits.h> > +#include <linux/clk-provider.h> > +#include <linux/err.h> > +#include <linux/export.h> > +#include <linux/io.h> > +#include <linux/iopoll.h> > +#include <linux/slab.h> > +#include <linux/jiffies.h> > + > +#include "clk.h" > + > +#define PLL_CTRL 0x0 > +#define CLKMUX_BYPASS BIT(2) > +#define CLKMUX_EN BIT(1) > +#define POWERUP_MASK BIT(0) > + > +#define PLL_ANA_PRG 0x10 > +#define PLL_SPREAD_SPECTRUM 0x30 > + > +#define PLL_NUMERATOR 0x40 > +#define PLL_MFN_MASK GENMASK(31, 2) > +#define PLL_MFN_SHIFT 2 > + > +#define PLL_DENOMINATOR 0x50 > +#define PLL_MFD_MASK GENMASK(29, 0) > + > +#define PLL_DIV 0x60 > +#define PLL_MFI_MASK GENMASK(24, 16) > +#define PLL_MFI_SHIFT 16 > +#define PLL_RDIV_MASK GENMASK(15, 13) > +#define PLL_RDIV_SHIFT 13 > +#define PLL_ODIV_MASK GENMASK(7, 0) > + > +#define PLL_DFS_CTRL(x) (0x70 + (x) * 0x10) > + > +#define PLL_STATUS 0xF0 > +#define LOCK_STATUS BIT(0) > + > +#define DFS_STATUS 0xF4 > + > +#define LOCK_TIMEOUT_US 200 > + > +#define PLL_FRACN_GP(_rate, _mfi, _mfn, _mfd, _rdiv, _odiv) \ > + { \ > + .rate = (_rate), \ > + .mfi = (_mfi), \ > + .mfn = (_mfn), \ > + .mfd = (_mfd), \ > + .rdiv = (_rdiv), \ > + .odiv = (_odiv), \ > + } > + > +struct clk_fracn_gppll { > + struct clk_hw hw; > + void __iomem *base; > + const struct imx_fracn_gppll_rate_table *rate_table; > + int rate_count; > +}; > + > +#define to_clk_fracn_gppll(_hw) container_of(_hw, struct clk_fracn_gppll, hw) > + > +/* > + * Fvco =
Hi, Sorry for the late review, but this PLL seems to have some copy-pasted code I just cleaned up in another PLL, so I thought I have a closer look. On Wed, Feb 23, 2022 at 02:43:57PM +0800, Peng Fan (OSS) wrote: > From: Peng Fan <peng.fan@nxp.com> > > This PLL module is a Fractional-N synthesizer, > supporting 30-bit numerator and denominator. Numerator is a signed > number. It has feature to adjust fractional portion of feedback > divider dynamically. This fracn gppll is used in i.MX93. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- > drivers/clk/imx/Makefile | 1 + > drivers/clk/imx/clk-fracn-gppll.c | 328 ++++++++++++++++++++++++++++++ > drivers/clk/imx/clk.h | 21 ++ > 3 files changed, 350 insertions(+) > create mode 100644 drivers/clk/imx/clk-fracn-gppll.c > > diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile > index 36c04922d789..60c8a4bb7574 100644 > --- a/drivers/clk/imx/Makefile > +++ b/drivers/clk/imx/Makefile > @@ -5,6 +5,7 @@ mxc-clk-objs += clk-busy.o > mxc-clk-objs += clk-composite-7ulp.o > mxc-clk-objs += clk-composite-8m.o > mxc-clk-objs += clk-composite-93.o > +mxc-clk-objs += clk-fracn-gppll.o > mxc-clk-objs += clk-cpu.o > mxc-clk-objs += clk-divider-gate.o > mxc-clk-objs += clk-fixup-div.o > diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c > new file mode 100644 > index 000000000000..6c9946a4bdb7 > --- /dev/null > +++ b/drivers/clk/imx/clk-fracn-gppll.c > @@ -0,0 +1,328 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright 2021 NXP > + */ > + > +#include <linux/bits.h> > +#include <linux/clk-provider.h> > +#include <linux/err.h> > +#include <linux/export.h> > +#include <linux/io.h> > +#include <linux/iopoll.h> > +#include <linux/slab.h> > +#include <linux/jiffies.h> > + > +#include "clk.h" > + > +#define PLL_CTRL 0x0 > +#define CLKMUX_BYPASS BIT(2) > +#define CLKMUX_EN BIT(1) > +#define POWERUP_MASK BIT(0) > + > +#define PLL_ANA_PRG 0x10 > +#define PLL_SPREAD_SPECTRUM 0x30 > + > +#define PLL_NUMERATOR 0x40 > +#define PLL_MFN_MASK GENMASK(31, 2) > +#define PLL_MFN_SHIFT 2 > + > +#define PLL_DENOMINATOR 0x50 > +#define PLL_MFD_MASK GENMASK(29, 0) > + > +#define PLL_DIV 0x60 > +#define PLL_MFI_MASK GENMASK(24, 16) > +#define PLL_MFI_SHIFT 16 > +#define PLL_RDIV_MASK GENMASK(15, 13) > +#define PLL_RDIV_SHIFT 13 > +#define PLL_ODIV_MASK GENMASK(7, 0) > + > +#define PLL_DFS_CTRL(x) (0x70 + (x) * 0x10) > + > +#define PLL_STATUS 0xF0 > +#define LOCK_STATUS BIT(0) > + > +#define DFS_STATUS 0xF4 > + > +#define LOCK_TIMEOUT_US 200 > + > +#define PLL_FRACN_GP(_rate, _mfi, _mfn, _mfd, _rdiv, _odiv) \ > + { \ > + .rate = (_rate), \ > + .mfi = (_mfi), \ > + .mfn = (_mfn), \ > + .mfd = (_mfd), \ > + .rdiv = (_rdiv), \ > + .odiv = (_odiv), \ > + } > + > +struct clk_fracn_gppll { > + struct clk_hw hw; > + void __iomem *base; > + const struct imx_fracn_gppll_rate_table *rate_table; > + int rate_count; > +}; > + > +#define to_clk_fracn_gppll(_hw) container_of(_hw, struct clk_fracn_gppll, hw) Consider using a static inline function instead. > + > +/* > + * Fvco =
On 22-02-23 11:43:08, Sascha Hauer wrote: > Hi, > > Sorry for the late review, but this PLL seems to have some copy-pasted > code I just cleaned up in another PLL, so I thought I have a closer > look. > Thanks for helping with the review, Sascha. Peng, I'll wait for these comments to be addressed then. > > On Wed, Feb 23, 2022 at 02:43:57PM +0800, Peng Fan (OSS) wrote: > > From: Peng Fan <peng.fan@nxp.com> > > > > This PLL module is a Fractional-N synthesizer, > > supporting 30-bit numerator and denominator. Numerator is a signed > > number. It has feature to adjust fractional portion of feedback > > divider dynamically. This fracn gppll is used in i.MX93. > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > > --- > > drivers/clk/imx/Makefile | 1 + > > drivers/clk/imx/clk-fracn-gppll.c | 328 ++++++++++++++++++++++++++++++ > > drivers/clk/imx/clk.h | 21 ++ > > 3 files changed, 350 insertions(+) > > create mode 100644 drivers/clk/imx/clk-fracn-gppll.c > > > > diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile > > index 36c04922d789..60c8a4bb7574 100644 > > --- a/drivers/clk/imx/Makefile > > +++ b/drivers/clk/imx/Makefile > > @@ -5,6 +5,7 @@ mxc-clk-objs += clk-busy.o > > mxc-clk-objs += clk-composite-7ulp.o > > mxc-clk-objs += clk-composite-8m.o > > mxc-clk-objs += clk-composite-93.o > > +mxc-clk-objs += clk-fracn-gppll.o > > mxc-clk-objs += clk-cpu.o > > mxc-clk-objs += clk-divider-gate.o > > mxc-clk-objs += clk-fixup-div.o > > diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c > > new file mode 100644 > > index 000000000000..6c9946a4bdb7 > > --- /dev/null > > +++ b/drivers/clk/imx/clk-fracn-gppll.c > > @@ -0,0 +1,328 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright 2021 NXP > > + */ > > + > > +#include <linux/bits.h> > > +#include <linux/clk-provider.h> > > +#include <linux/err.h> > > +#include <linux/export.h> > > +#include <linux/io.h> > > +#include <linux/iopoll.h> > > +#include <linux/slab.h> > > +#include <linux/jiffies.h> > > + > > +#include "clk.h" > > + > > +#define PLL_CTRL 0x0 > > +#define CLKMUX_BYPASS BIT(2) > > +#define CLKMUX_EN BIT(1) > > +#define POWERUP_MASK BIT(0) > > + > > +#define PLL_ANA_PRG 0x10 > > +#define PLL_SPREAD_SPECTRUM 0x30 > > + > > +#define PLL_NUMERATOR 0x40 > > +#define PLL_MFN_MASK GENMASK(31, 2) > > +#define PLL_MFN_SHIFT 2 > > + > > +#define PLL_DENOMINATOR 0x50 > > +#define PLL_MFD_MASK GENMASK(29, 0) > > + > > +#define PLL_DIV 0x60 > > +#define PLL_MFI_MASK GENMASK(24, 16) > > +#define PLL_MFI_SHIFT 16 > > +#define PLL_RDIV_MASK GENMASK(15, 13) > > +#define PLL_RDIV_SHIFT 13 > > +#define PLL_ODIV_MASK GENMASK(7, 0) > > + > > +#define PLL_DFS_CTRL(x) (0x70 + (x) * 0x10) > > + > > +#define PLL_STATUS 0xF0 > > +#define LOCK_STATUS BIT(0) > > + > > +#define DFS_STATUS 0xF4 > > + > > +#define LOCK_TIMEOUT_US 200 > > + > > +#define PLL_FRACN_GP(_rate, _mfi, _mfn, _mfd, _rdiv, _odiv) \ > > + { \ > > + .rate = (_rate), \ > > + .mfi = (_mfi), \ > > + .mfn = (_mfn), \ > > + .mfd = (_mfd), \ > > + .rdiv = (_rdiv), \ > > + .odiv = (_odiv), \ > > + } > > + > > +struct clk_fracn_gppll { > > + struct clk_hw hw; > > + void __iomem *base; > > + const struct imx_fracn_gppll_rate_table *rate_table; > > + int rate_count; > > +}; > > + > > +#define to_clk_fracn_gppll(_hw) container_of(_hw, struct clk_fracn_gppll, hw) > > Consider using a static inline function instead. > > > + > > +/* > > + * Fvco =
Hi "Peng,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on next-20220217]
[also build test ERROR on v5.17-rc5]
[cannot apply to shawnguo/for-next robh/for-next clk/clk-next v5.17-rc5 v5.17-rc4 v5.17-rc3]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Peng-Fan-OSS/imx-add-i-MX93-clk-bindings-and-driver/20220223-144300
base: 3c30cf91b5ecc7272b3d2942ae0505dd8320b81c
config: microblaze-randconfig-r003-20220223 (https://download.01.org/0day-ci/archive/20220224/202202241151.VkSKqcfA-lkp@intel.com/config)
compiler: microblaze-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/93f29e11de75409d56c65d32c1bdafb50c9f6f51
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Peng-Fan-OSS/imx-add-i-MX93-clk-bindings-and-driver/20220223-144300
git checkout 93f29e11de75409d56c65d32c1bdafb50c9f6f51
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=microblaze SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
microblaze-linux-ld: drivers/clk/imx/clk-fracn-gppll.o: in function `clk_fracn_gppll_recalc_rate':
>> (.text+0x420): undefined reference to `__udivdi3'
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
Hi "Peng,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on next-20220217]
[also build test ERROR on v5.17-rc5]
[cannot apply to shawnguo/for-next robh/for-next clk/clk-next v5.17-rc5 v5.17-rc4 v5.17-rc3]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Peng-Fan-OSS/imx-add-i-MX93-clk-bindings-and-driver/20220223-144300
base: 3c30cf91b5ecc7272b3d2942ae0505dd8320b81c
config: nds32-randconfig-r026-20220223 (https://download.01.org/0day-ci/archive/20220224/202202241105.0bwJWaUv-lkp@intel.com/config)
compiler: nds32le-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/93f29e11de75409d56c65d32c1bdafb50c9f6f51
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Peng-Fan-OSS/imx-add-i-MX93-clk-bindings-and-driver/20220223-144300
git checkout 93f29e11de75409d56c65d32c1bdafb50c9f6f51
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=nds32 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
nds32le-linux-ld: drivers/clk/imx/clk-fracn-gppll.o: in function `clk_fracn_gppll_recalc_rate':
>> clk-fracn-gppll.c:(.text+0x228): undefined reference to `__udivdi3'
nds32le-linux-ld: clk-fracn-gppll.c:(.text+0x22c): undefined reference to `__udivdi3'
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 36c04922d789..60c8a4bb7574 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -5,6 +5,7 @@ mxc-clk-objs += clk-busy.o mxc-clk-objs += clk-composite-7ulp.o mxc-clk-objs += clk-composite-8m.o mxc-clk-objs += clk-composite-93.o +mxc-clk-objs += clk-fracn-gppll.o mxc-clk-objs += clk-cpu.o mxc-clk-objs += clk-divider-gate.o mxc-clk-objs += clk-fixup-div.o diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c new file mode 100644 index 000000000000..6c9946a4bdb7 --- /dev/null +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -0,0 +1,328 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2021 NXP + */ + +#include <linux/bits.h> +#include <linux/clk-provider.h> +#include <linux/err.h> +#include <linux/export.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/slab.h> +#include <linux/jiffies.h> + +#include "clk.h" + +#define PLL_CTRL 0x0 +#define CLKMUX_BYPASS BIT(2) +#define CLKMUX_EN BIT(1) +#define POWERUP_MASK BIT(0) + +#define PLL_ANA_PRG 0x10 +#define PLL_SPREAD_SPECTRUM 0x30 + +#define PLL_NUMERATOR 0x40 +#define PLL_MFN_MASK GENMASK(31, 2) +#define PLL_MFN_SHIFT 2 + +#define PLL_DENOMINATOR 0x50 +#define PLL_MFD_MASK GENMASK(29, 0) + +#define PLL_DIV 0x60 +#define PLL_MFI_MASK GENMASK(24, 16) +#define PLL_MFI_SHIFT 16 +#define PLL_RDIV_MASK GENMASK(15, 13) +#define PLL_RDIV_SHIFT 13 +#define PLL_ODIV_MASK GENMASK(7, 0) + +#define PLL_DFS_CTRL(x) (0x70 + (x) * 0x10) + +#define PLL_STATUS 0xF0 +#define LOCK_STATUS BIT(0) + +#define DFS_STATUS 0xF4 + +#define LOCK_TIMEOUT_US 200 + +#define PLL_FRACN_GP(_rate, _mfi, _mfn, _mfd, _rdiv, _odiv) \ + { \ + .rate = (_rate), \ + .mfi = (_mfi), \ + .mfn = (_mfn), \ + .mfd = (_mfd), \ + .rdiv = (_rdiv), \ + .odiv = (_odiv), \ + } + +struct clk_fracn_gppll { + struct clk_hw hw; + void __iomem *base; + const struct imx_fracn_gppll_rate_table *rate_table; + int rate_count; +}; + +#define to_clk_fracn_gppll(_hw) container_of(_hw, struct clk_fracn_gppll, hw) + +/* + * Fvco =