| Message ID | 20220223185606.3941-1-tdas@codeaurora.org (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Headers | show |
| Series | [v2,1/2] clk: qcom: gdsc: Add support to update GDSC transition delay | expand |
Quoting Taniya Das (2022-02-23 10:56:05) > GDSCs have multiple transition delays which are used for the GDSC FSM > states. Older targets/designs required these values to be updated from > gdsc code to certain default values for the FSM state to work as > expected. But on the newer targets/designs the values updated from the > GDSC driver can hamper the FSM state to not work as expected. > > On SC7180 we observe black screens because the gdsc is being > enabled/disabled very rapidly and the GDSC FSM state does not work as > expected. This is due to the fact that the GDSC reset value is being > updated from SW. > > Thus add support to update the transition delay from the clock > controller gdscs as required. > > Fixes: 45dd0e55317cc ("clk: qcom: Add support for GDSCs) > Signed-off-by: Taniya Das <tdas@codeaurora.org> > --- Looks like I need to apply this for clk-fixes. Please keep Bjorn on Cc next time for awareness.
Quoting Taniya Das (2022-02-23 10:56:05) > GDSCs have multiple transition delays which are used for the GDSC FSM > states. Older targets/designs required these values to be updated from > gdsc code to certain default values for the FSM state to work as > expected. But on the newer targets/designs the values updated from the > GDSC driver can hamper the FSM state to not work as expected. > > On SC7180 we observe black screens because the gdsc is being > enabled/disabled very rapidly and the GDSC FSM state does not work as > expected. This is due to the fact that the GDSC reset value is being > updated from SW. > > Thus add support to update the transition delay from the clock > controller gdscs as required. > > Fixes: 45dd0e55317cc ("clk: qcom: Add support for GDSCs) > Signed-off-by: Taniya Das <tdas@codeaurora.org> Applied to clk-fixes with Bjorn's reviewed-by. One note below, please make this improvement. > diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h > index d7cc4c21a9d4..ad313d7210bd 100644 > --- a/drivers/clk/qcom/gdsc.h > +++ b/drivers/clk/qcom/gdsc.h > @@ -1,6 +1,6 @@ > /* SPDX-License-Identifier: GPL-2.0-only */ > /* > - * Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved. > + * Copyright (c) 2015, 2017-2018, 2022, The Linux Foundation. All rights reserved. > */ > > #ifndef __QCOM_GDSC_H__ > @@ -22,6 +22,9 @@ struct reset_controller_dev; > * @cxcs: offsets of branch registers to toggle mem/periph bits in > * @cxc_count: number of @cxcs > * @pwrsts: Possible powerdomain power states > + * @en_rest_wait_val: transition delay value for receiving enr ack signal > + * @en_few_wait_val: transition delay value for receiving enf ack signal > + * @clk_dis_wait_val: transition delay value for halting clock > * @resets: ids of resets associated with this gdsc > * @reset_count: number of @resets > * @rcdev: reset controller > @@ -36,6 +39,9 @@ struct gdsc { > unsigned int clamp_io_ctrl; > unsigned int *cxcs; > unsigned int cxc_count; > + unsigned int en_rest_wait_val; > + unsigned int en_few_wait_val; > + unsigned int clk_dis_wait_val; Bjorn pointed out the usage of unsigned int is too big. These are 4-bits wide fields in the hardware. We should pack these into a u16 and then shift it and write it into place if it is non-zero. That means the driver author has to know all the values, but that sounds OK to me given that they're already changing something from the hardware defaults. This will save space in the vmlinux for however many gdscs there are declared. We should have a macro for this too so we can pack all the values together and then just write it out directly without having to know the shifts and stuff. #define GDSC_WAIT_VALS(en_rest, en_few, clk_dis)
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index 7e1dd8ccfa38..44520efc6c72 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2015, 2017-2018, 2022, The Linux Foundation. All rights reserved. */ #include <linux/bitops.h> @@ -35,9 +35,14 @@ #define CFG_GDSCR_OFFSET 0x4 /* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */ -#define EN_REST_WAIT_VAL (0x2 << 20) -#define EN_FEW_WAIT_VAL (0x8 << 16) -#define CLK_DIS_WAIT_VAL (0x2 << 12) +#define EN_REST_WAIT_VAL 0x2 +#define EN_FEW_WAIT_VAL 0x8 +#define CLK_DIS_WAIT_VAL 0x2 + +/* Transition delay shifts */ +#define EN_REST_WAIT_SHIFT 20 +#define EN_FEW_WAIT_SHIFT 16 +#define CLK_DIS_WAIT_SHIFT 12 #define RETAIN_MEM BIT(14) #define RETAIN_PERIPH BIT(13) @@ -380,7 +385,18 @@ static int gdsc_init(struct gdsc *sc) */ mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK | EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK; - val = EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL; + + if (!sc->en_rest_wait_val) + sc->en_rest_wait_val = EN_REST_WAIT_VAL; + if (!sc->en_few_wait_val) + sc->en_few_wait_val = EN_FEW_WAIT_VAL; + if (!sc->clk_dis_wait_val) + sc->clk_dis_wait_val = CLK_DIS_WAIT_VAL; + + val = sc->en_rest_wait_val << EN_REST_WAIT_SHIFT | + sc->en_few_wait_val << EN_FEW_WAIT_SHIFT | + sc->clk_dis_wait_val << CLK_DIS_WAIT_SHIFT; + ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val); if (ret) return ret; diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index d7cc4c21a9d4..ad313d7210bd 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2015, 2017-2018, 2022, The Linux Foundation. All rights reserved. */ #ifndef __QCOM_GDSC_H__ @@ -22,6 +22,9 @@ struct reset_controller_dev; * @cxcs: offsets of branch registers to toggle mem/periph bits in * @cxc_count: number of @cxcs * @pwrsts: Possible powerdomain power states + * @en_rest_wait_val: transition delay value for receiving enr ack signal + * @en_few_wait_val: transition delay value for receiving enf ack signal + * @clk_dis_wait_val: transition delay value for halting clock * @resets: ids of resets associated with this gdsc * @reset_count: number of @resets * @rcdev: reset controller @@ -36,6 +39,9 @@ struct gdsc { unsigned int clamp_io_ctrl; unsigned int *cxcs; unsigned int cxc_count; + unsigned int en_rest_wait_val; + unsigned int en_few_wait_val; + unsigned int clk_dis_wait_val; const u8 pwrsts; /* Powerdomain allowable state bitfields */ #define PWRSTS_OFF BIT(0)
GDSCs have multiple transition delays which are used for the GDSC FSM states. Older targets/designs required these values to be updated from gdsc code to certain default values for the FSM state to work as expected. But on the newer targets/designs the values updated from the GDSC driver can hamper the FSM state to not work as expected. On SC7180 we observe black screens because the gdsc is being enabled/disabled very rapidly and the GDSC FSM state does not work as expected. This is due to the fact that the GDSC reset value is being updated from SW. Thus add support to update the transition delay from the clock controller gdscs as required. Fixes: 45dd0e55317cc ("clk: qcom: Add support for GDSCs) Signed-off-by: Taniya Das <tdas@codeaurora.org> --- [v2] * Add 3 transition delays and update the default values in case of non-zero value. * Update the delays from mdss gdsc in the corresponding display clock controllers. drivers/clk/qcom/gdsc.c | 26 +++++++++++++++++++++----- drivers/clk/qcom/gdsc.h | 8 +++++++- 2 files changed, 28 insertions(+), 6 deletions(-) -- Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.