| Message ID | 1645505785-2271-2-git-send-email-quic_rohiagar@quicinc.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 2cabc45237659cb3b0294c8b8ae12f5fd0dad28d |
| Headers | show |
| Series | Add APCS support for SDX65 | expand |
On Tue, 22 Feb 2022 10:26:21 +0530, Rohit Agarwal wrote: > Add information for Cortex A7 PLL clock in Qualcomm > platform SDX65. > > Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> > --- > Documentation/devicetree/bindings/clock/qcom,a7pll.yaml | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Acked-by: Rob Herring <robh@kernel.org>
Quoting Rohit Agarwal (2022-02-21 20:56:21) > Add information for Cortex A7 PLL clock in Qualcomm > platform SDX65. > > Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> > --- Reviewed-by: Stephen Boyd <sboyd@kernel.org>
On Tue, Feb 22, 2022 at 10:26:21AM +0530, Rohit Agarwal wrote: > Add information for Cortex A7 PLL clock in Qualcomm > platform SDX65. > > Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Thanks, Mani > --- > Documentation/devicetree/bindings/clock/qcom,a7pll.yaml | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml > index 8666e99..0e96f69 100644 > --- a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml > +++ b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml > @@ -10,7 +10,7 @@ maintainers: > - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > description: > - The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high > + The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high > frequency clock to the CPU. > > properties: > -- > 2.7.4 >
diff --git a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml index 8666e99..0e96f69 100644 --- a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml @@ -10,7 +10,7 @@ maintainers: - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> description: - The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high + The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high frequency clock to the CPU. properties:
Add information for Cortex A7 PLL clock in Qualcomm platform SDX65. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> --- Documentation/devicetree/bindings/clock/qcom,a7pll.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)