diff mbox series

[v6,08/14] target/riscv: rvk: add support for sha256 related instructions in zknh extension

Message ID 20220227142553.25815-9-liweiwei@iscas.ac.cn (mailing list archive)
State New, archived
Headers show
Series support subsets of scalar crypto extension | expand

Commit Message

Weiwei Li Feb. 27, 2022, 2:25 p.m. UTC 
- add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions

Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/crypto_helper.c            | 31 +++++++++++++
 target/riscv/helper.h                   |  5 +++
 target/riscv/insn32.decode              |  5 +++
 target/riscv/insn_trans/trans_rvk.c.inc | 58 +++++++++++++++++++++++++
 4 files changed, 99 insertions(+)

Comments

Richard Henderson Feb. 27, 2022, 7:21 p.m. UTC | #1 
On 2/27/22 04:25, Weiwei Li wrote:
>   - add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions
> 
> Co-authored-by: Zewen Ye <lustrew@foxmail.com>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
>   target/riscv/crypto_helper.c            | 31 +++++++++++++
>   target/riscv/helper.h                   |  5 +++
>   target/riscv/insn32.decode              |  5 +++
>   target/riscv/insn_trans/trans_rvk.c.inc | 58 +++++++++++++++++++++++++
>   4 files changed, 99 insertions(+)
> 
> diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
> index 9e56668627..f5ffc262f2 100644
> --- a/target/riscv/crypto_helper.c
> +++ b/target/riscv/crypto_helper.c
> @@ -272,4 +272,35 @@ target_ulong HELPER(aes64im)(target_ulong rs1)
>   
>       return result;
>   }
> +
> +#define ROR32(a, amt) ((a << (-amt & 31)) | (a >> (amt & 31)))

We already have a ror32 function.  However...

> +target_ulong HELPER(sha256sig0)(target_ulong rs1)
> +{
> +    uint32_t a = rs1;
> +
> +    return sext_xlen(ROR32(a, 7) ^ ROR32(a, 18) ^ (a >> 3));
> +}
> +
> +target_ulong HELPER(sha256sig1)(target_ulong rs1)
> +{
> +    uint32_t a = rs1;
> +
> +    return sext_xlen(ROR32(a, 17) ^ ROR32(a, 19) ^ (a >> 10));
> +}
> +
> +target_ulong HELPER(sha256sum0)(target_ulong rs1)
> +{
> +    uint32_t a = rs1;
> +
> +    return sext_xlen(ROR32(a, 2) ^ ROR32(a, 13) ^ ROR32(a, 22));
> +}
> +
> +target_ulong HELPER(sha256sum1)(target_ulong rs1)
> +{
> +    uint32_t a = rs1;
> +
> +    return sext_xlen(ROR32(a, 6) ^ ROR32(a, 11) ^ ROR32(a, 25));
> +}

All of these functions are quite small, and could easily be generated inline.

     tcg_gen_trunc_tl_i32(a, reg);
     tcg_gen_rotri_i32(t1, a, 7);
     tcg_gen_rotri_i32(t2, a, 18);
     tcg_gen_xor_i32(t1, t1, t2);
     tcg_gen_shri_i32(t2, a, 3);
     tcg_gen_xor_i32(t1, t1, t2);
     tcg_gen_ext_i32_tl(reg, t1);

> +static bool trans_sha256sig0(DisasContext *ctx, arg_sha256sig0 *a)
> +{
> +    REQUIRE_ZKNH(ctx);
> +
> +    TCGv dest = dest_gpr(ctx, a->rd);
> +    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
> +
> +    gen_helper_sha256sig0(dest, src1);
> +    gen_set_gpr(ctx, a->rd, dest);
> +
> +    return true;
> +}

gen_unary, etc.


r~
Weiwei Li Feb. 28, 2022, 3:11 a.m. UTC | #2 
在 2022/2/28 上午3:21, Richard Henderson 写道:
> On 2/27/22 04:25, Weiwei Li wrote:
>>   - add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions
>>
>> Co-authored-by: Zewen Ye <lustrew@foxmail.com>
>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>> ---
>>   target/riscv/crypto_helper.c            | 31 +++++++++++++
>>   target/riscv/helper.h                   |  5 +++
>>   target/riscv/insn32.decode              |  5 +++
>>   target/riscv/insn_trans/trans_rvk.c.inc | 58 +++++++++++++++++++++++++
>>   4 files changed, 99 insertions(+)
>>
>> diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
>> index 9e56668627..f5ffc262f2 100644
>> --- a/target/riscv/crypto_helper.c
>> +++ b/target/riscv/crypto_helper.c
>> @@ -272,4 +272,35 @@ target_ulong HELPER(aes64im)(target_ulong rs1)
>>         return result;
>>   }
>> +
>> +#define ROR32(a, amt) ((a << (-amt & 31)) | (a >> (amt & 31)))
>
> We already have a ror32 function.  However...
OK. I'll change to use it.
>
>> +target_ulong HELPER(sha256sig0)(target_ulong rs1)
>> +{
>> +    uint32_t a = rs1;
>> +
>> +    return sext_xlen(ROR32(a, 7) ^ ROR32(a, 18) ^ (a >> 3));
>> +}
>> +
>> +target_ulong HELPER(sha256sig1)(target_ulong rs1)
>> +{
>> +    uint32_t a = rs1;
>> +
>> +    return sext_xlen(ROR32(a, 17) ^ ROR32(a, 19) ^ (a >> 10));
>> +}
>> +
>> +target_ulong HELPER(sha256sum0)(target_ulong rs1)
>> +{
>> +    uint32_t a = rs1;
>> +
>> +    return sext_xlen(ROR32(a, 2) ^ ROR32(a, 13) ^ ROR32(a, 22));
>> +}
>> +
>> +target_ulong HELPER(sha256sum1)(target_ulong rs1)
>> +{
>> +    uint32_t a = rs1;
>> +
>> +    return sext_xlen(ROR32(a, 6) ^ ROR32(a, 11) ^ ROR32(a, 25));
>> +}
>
> All of these functions are quite small, and could easily be generated 
> inline.
>
>     tcg_gen_trunc_tl_i32(a, reg);
>     tcg_gen_rotri_i32(t1, a, 7);
>     tcg_gen_rotri_i32(t2, a, 18);
>     tcg_gen_xor_i32(t1, t1, t2);
>     tcg_gen_shri_i32(t2, a, 3);
>     tcg_gen_xor_i32(t1, t1, t2);
>     tcg_gen_ext_i32_tl(reg, t1);
OK. I'll change to this.
>
>> +static bool trans_sha256sig0(DisasContext *ctx, arg_sha256sig0 *a)
>> +{
>> +    REQUIRE_ZKNH(ctx);
>> +
>> +    TCGv dest = dest_gpr(ctx, a->rd);
>> +    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
>> +
>> +    gen_helper_sha256sig0(dest, src1);
>> +    gen_set_gpr(ctx, a->rd, dest);
>> +
>> +    return true;
>> +}
>
> gen_unary, etc.

OK. I'll fix it.

Regards,

Weiwei Li

>
>
> r~
diff mbox series

Patch

diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
index 9e56668627..f5ffc262f2 100644
--- a/target/riscv/crypto_helper.c
+++ b/target/riscv/crypto_helper.c
@@ -272,4 +272,35 @@  target_ulong HELPER(aes64im)(target_ulong rs1)
 
     return result;
 }
+
+#define ROR32(a, amt) ((a << (-amt & 31)) | (a >> (amt & 31)))
+
+target_ulong HELPER(sha256sig0)(target_ulong rs1)
+{
+    uint32_t a = rs1;
+
+    return sext_xlen(ROR32(a, 7) ^ ROR32(a, 18) ^ (a >> 3));
+}
+
+target_ulong HELPER(sha256sig1)(target_ulong rs1)
+{
+    uint32_t a = rs1;
+
+    return sext_xlen(ROR32(a, 17) ^ ROR32(a, 19) ^ (a >> 10));
+}
+
+target_ulong HELPER(sha256sum0)(target_ulong rs1)
+{
+    uint32_t a = rs1;
+
+    return sext_xlen(ROR32(a, 2) ^ ROR32(a, 13) ^ ROR32(a, 22));
+}
+
+target_ulong HELPER(sha256sum1)(target_ulong rs1)
+{
+    uint32_t a = rs1;
+
+    return sext_xlen(ROR32(a, 6) ^ ROR32(a, 11) ^ ROR32(a, 25));
+}
+#undef ROR32
 #undef sext_xlen
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 040b771eb6..898d093ae9 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1129,3 +1129,8 @@  DEF_HELPER_2(aes64dsm, tl, tl, tl)
 DEF_HELPER_2(aes64ks2, tl, tl, tl)
 DEF_HELPER_2(aes64ks1i, tl, tl, tl)
 DEF_HELPER_1(aes64im, tl, tl)
+
+DEF_HELPER_1(sha256sig0, tl, tl)
+DEF_HELPER_1(sha256sig1, tl, tl)
+DEF_HELPER_1(sha256sum0, tl, tl)
+DEF_HELPER_1(sha256sum1, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index bf6a8797a2..f86745edcb 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -854,3 +854,8 @@  aes64esm    00 11011 ..... ..... 000 ..... 0110011 @r
 # *** RV64 Zkne/zknd Standard Extension ***
 aes64ks2    01 11111 ..... ..... 000 ..... 0110011 @r
 aes64ks1i   00 11000 1.... ..... 001 ..... 0010011 %rnum %rs1 %rd
+# *** RV32 Zknh Standard Extension ***
+sha256sig0  00 01000 00010 ..... 001 ..... 0010011 @r2
+sha256sig1  00 01000 00011 ..... 001 ..... 0010011 @r2
+sha256sum0  00 01000 00000 ..... 001 ..... 0010011 @r2
+sha256sum1  00 01000 00001 ..... 001 ..... 0010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
index 3dc855fd3c..ce29eaa2f4 100644
--- a/target/riscv/insn_trans/trans_rvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
@@ -29,6 +29,12 @@ 
     }                                           \
 } while (0)
 
+#define REQUIRE_ZKNH(ctx) do {                  \
+    if (!ctx->cfg_ptr->ext_zknh) {    \
+        return false;                           \
+    }                                           \
+} while (0)
+
 static bool trans_aes32esmi(DisasContext *ctx, arg_aes32esmi *a)
 {
     REQUIRE_ZKNE(ctx);
@@ -194,3 +200,55 @@  static bool trans_aes64im(DisasContext *ctx, arg_aes64im *a)
 
     return true;
 }
+
+static bool trans_sha256sig0(DisasContext *ctx, arg_sha256sig0 *a)
+{
+    REQUIRE_ZKNH(ctx);
+
+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+    gen_helper_sha256sig0(dest, src1);
+    gen_set_gpr(ctx, a->rd, dest);
+
+    return true;
+}
+
+static bool trans_sha256sig1(DisasContext *ctx, arg_sha256sig1 *a)
+{
+    REQUIRE_ZKNH(ctx);
+
+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+    gen_helper_sha256sig1(dest, src1);
+    gen_set_gpr(ctx, a->rd, dest);
+
+    return true;
+}
+
+static bool trans_sha256sum0(DisasContext *ctx, arg_sha256sum0 *a)
+{
+    REQUIRE_ZKNH(ctx);
+
+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+    gen_helper_sha256sum0(dest, src1);
+    gen_set_gpr(ctx, a->rd, dest);
+
+    return true;
+}
+
+static bool trans_sha256sum1(DisasContext *ctx, arg_sha256sum1 *a)
+{
+    REQUIRE_ZKNH(ctx);
+
+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+    gen_helper_sha256sum1(dest, src1);
+    gen_set_gpr(ctx, a->rd, dest);
+
+    return true;
+}