| Message ID | 20220215184651.12168-1-alyssa.rosenzweig@collabora.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] soc: mediatek: mtk-infracfg: Disable ACP on MT8192 | expand |
Il 15/02/22 19:46, Alyssa Rosenzweig ha scritto: > MT8192 contains an experimental Accelerator Coherency Port > implementation, which does not work correctly but was unintentionally > enabled by default. For correct operation of the GPU, we must set a > chicken bit disabling ACP on MT8192. > > Adapted from the following downstream change to the out-of-tree, legacy > Mali GPU driver: > > https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2781271/5 > > Note this change is required for both Panfrost and the legacy kernel > driver. Hello Alyssa, the v2 note should not get inside the commit message, even though they should be on the patch to provide context. Look at the example... > > v2: Move the change from clk-mt8192.c to mtk-infracfg.c (Robin). > Although it does not make sense to add this platform-specific hack to > the GPU driver, it has nothing to do with clocks. We already have > mtk-infracfg.c to manage other infracfg bits; the ACP disable should > live there too. > > Co-developed-by: Robin Murphy <robin.murphy@arm.com> > Signed-off-by: Robin Murphy <robin.murphy@arm.com> > Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> > Cc: Nick Fan <Nick.Fan@mediatek.com> > Cc: Nicolas Boichat <drinkcat@chromium.org> > Cc: Chen-Yu Tsai <wenst@chromium.org> > Cc: Stephen Boyd <sboyd@kernel.org> > Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- v2: Move the change from clk-mt8192.c to mtk-infracfg.c (Robin). ^^^ put it here, after the "---" :) Anyway, Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > drivers/soc/mediatek/mtk-infracfg.c | 19 +++++++++++++++++++ > include/linux/soc/mediatek/infracfg.h | 3 +++ > 2 files changed, 22 insertions(+) > > diff --git a/drivers/soc/mediatek/mtk-infracfg.c b/drivers/soc/mediatek/mtk-infracfg.c > index 0590b68e0d78..2acf19676af2 100644 > --- a/drivers/soc/mediatek/mtk-infracfg.c > +++ b/drivers/soc/mediatek/mtk-infracfg.c > @@ -6,6 +6,7 @@ > #include <linux/export.h> > #include <linux/jiffies.h> > #include <linux/regmap.h> > +#include <linux/mfd/syscon.h> > #include <linux/soc/mediatek/infracfg.h> > #include <asm/processor.h> > > @@ -72,3 +73,21 @@ int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, > > return ret; > } > + > +static int __init mtk_infracfg_init(void) > +{ > + struct regmap *infracfg; > + > + /* > + * MT8192 has an experimental path to route GPU traffic to the DSU's > + * Accelerator Coherency Port, which is inadvertently enabled by > + * default. It turns out not to work, so disable it to prevent spurious > + * GPU faults. > + */ > + infracfg = syscon_regmap_lookup_by_compatible("mediatek,mt8192-infracfg"); > + if (!IS_ERR(infracfg)) > + regmap_set_bits(infracfg, MT8192_INFRA_CTRL, > + MT8192_INFRA_CTRL_DISABLE_MFG2ACP); > + return 0; > +} > +postcore_initcall(mtk_infracfg_init); > diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h > index d858e0bab7a2..fcbbd0dd5e55 100644 > --- a/include/linux/soc/mediatek/infracfg.h > +++ b/include/linux/soc/mediatek/infracfg.h > @@ -229,6 +229,9 @@ > #define INFRA_TOPAXI_PROTECTEN_SET 0x0260 > #define INFRA_TOPAXI_PROTECTEN_CLR 0x0264 > > +#define MT8192_INFRA_CTRL 0x290 > +#define MT8192_INFRA_CTRL_DISABLE_MFG2ACP BIT(9) > + > #define REG_INFRA_MISC 0xf00 > #define F_DDR_4GB_SUPPORT_EN BIT(13) >
Hi all, On 17/02/2022 11:40, AngeloGioacchino Del Regno wrote: > Il 15/02/22 19:46, Alyssa Rosenzweig ha scritto: >> MT8192 contains an experimental Accelerator Coherency Port >> implementation, which does not work correctly but was unintentionally >> enabled by default. For correct operation of the GPU, we must set a >> chicken bit disabling ACP on MT8192. >> >> Adapted from the following downstream change to the out-of-tree, legacy >> Mali GPU driver: >> >> https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2781271/5 >> >> >> Note this change is required for both Panfrost and the legacy kernel >> driver. > > Hello Alyssa, > the v2 note should not get inside the commit message, even though they should be > on the patch to provide context. > Look at the example... > I think the most obvious would be to disable the ACP in the boot firmware. But as we can't control that, we will need to work around it. So: Patch applied. I fixed the commit message by deleting the v2 note. Thanks everybody for figuring out what to do about that. Regards, Matthias >> >> v2: Move the change from clk-mt8192.c to mtk-infracfg.c (Robin). >> Although it does not make sense to add this platform-specific hack to >> the GPU driver, it has nothing to do with clocks. We already have >> mtk-infracfg.c to manage other infracfg bits; the ACP disable should >> live there too. >> >> Co-developed-by: Robin Murphy <robin.murphy@arm.com> >> Signed-off-by: Robin Murphy <robin.murphy@arm.com> >> Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> >> Cc: Nick Fan <Nick.Fan@mediatek.com> >> Cc: Nicolas Boichat <drinkcat@chromium.org> >> Cc: Chen-Yu Tsai <wenst@chromium.org> >> Cc: Stephen Boyd <sboyd@kernel.org> >> Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> >> --- > > v2: Move the change from clk-mt8192.c to mtk-infracfg.c (Robin). > > ^^^ put it here, after the "---" :) > > Anyway, > Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > >> drivers/soc/mediatek/mtk-infracfg.c | 19 +++++++++++++++++++ >> include/linux/soc/mediatek/infracfg.h | 3 +++ >> 2 files changed, 22 insertions(+) >> >> diff --git a/drivers/soc/mediatek/mtk-infracfg.c >> b/drivers/soc/mediatek/mtk-infracfg.c >> index 0590b68e0d78..2acf19676af2 100644 >> --- a/drivers/soc/mediatek/mtk-infracfg.c >> +++ b/drivers/soc/mediatek/mtk-infracfg.c >> @@ -6,6 +6,7 @@ >> #include <linux/export.h> >> #include <linux/jiffies.h> >> #include <linux/regmap.h> >> +#include <linux/mfd/syscon.h> >> #include <linux/soc/mediatek/infracfg.h> >> #include <asm/processor.h> >> @@ -72,3 +73,21 @@ int mtk_infracfg_clear_bus_protection(struct regmap >> *infracfg, u32 mask, >> return ret; >> } >> + >> +static int __init mtk_infracfg_init(void) >> +{ >> + struct regmap *infracfg; >> + >> + /* >> + * MT8192 has an experimental path to route GPU traffic to the DSU's >> + * Accelerator Coherency Port, which is inadvertently enabled by >> + * default. It turns out not to work, so disable it to prevent spurious >> + * GPU faults. >> + */ >> + infracfg = syscon_regmap_lookup_by_compatible("mediatek,mt8192-infracfg"); >> + if (!IS_ERR(infracfg)) >> + regmap_set_bits(infracfg, MT8192_INFRA_CTRL, >> + MT8192_INFRA_CTRL_DISABLE_MFG2ACP); >> + return 0; >> +} >> +postcore_initcall(mtk_infracfg_init); >> diff --git a/include/linux/soc/mediatek/infracfg.h >> b/include/linux/soc/mediatek/infracfg.h >> index d858e0bab7a2..fcbbd0dd5e55 100644 >> --- a/include/linux/soc/mediatek/infracfg.h >> +++ b/include/linux/soc/mediatek/infracfg.h >> @@ -229,6 +229,9 @@ >> #define INFRA_TOPAXI_PROTECTEN_SET 0x0260 >> #define INFRA_TOPAXI_PROTECTEN_CLR 0x0264 >> +#define MT8192_INFRA_CTRL 0x290 >> +#define MT8192_INFRA_CTRL_DISABLE_MFG2ACP BIT(9) >> + >> #define REG_INFRA_MISC 0xf00 >> #define F_DDR_4GB_SUPPORT_EN BIT(13) > >
> Patch applied. I fixed the commit message by deleting the v2 note.
Thank you!
diff --git a/drivers/soc/mediatek/mtk-infracfg.c b/drivers/soc/mediatek/mtk-infracfg.c index 0590b68e0d78..2acf19676af2 100644 --- a/drivers/soc/mediatek/mtk-infracfg.c +++ b/drivers/soc/mediatek/mtk-infracfg.c @@ -6,6 +6,7 @@ #include <linux/export.h> #include <linux/jiffies.h> #include <linux/regmap.h> +#include <linux/mfd/syscon.h> #include <linux/soc/mediatek/infracfg.h> #include <asm/processor.h> @@ -72,3 +73,21 @@ int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, return ret; } + +static int __init mtk_infracfg_init(void) +{ + struct regmap *infracfg; + + /* + * MT8192 has an experimental path to route GPU traffic to the DSU's + * Accelerator Coherency Port, which is inadvertently enabled by + * default. It turns out not to work, so disable it to prevent spurious + * GPU faults. + */ + infracfg = syscon_regmap_lookup_by_compatible("mediatek,mt8192-infracfg"); + if (!IS_ERR(infracfg)) + regmap_set_bits(infracfg, MT8192_INFRA_CTRL, + MT8192_INFRA_CTRL_DISABLE_MFG2ACP); + return 0; +} +postcore_initcall(mtk_infracfg_init); diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h index d858e0bab7a2..fcbbd0dd5e55 100644 --- a/include/linux/soc/mediatek/infracfg.h +++ b/include/linux/soc/mediatek/infracfg.h @@ -229,6 +229,9 @@ #define INFRA_TOPAXI_PROTECTEN_SET 0x0260 #define INFRA_TOPAXI_PROTECTEN_CLR 0x0264 +#define MT8192_INFRA_CTRL 0x290 +#define MT8192_INFRA_CTRL_DISABLE_MFG2ACP BIT(9) + #define REG_INFRA_MISC 0xf00 #define F_DDR_4GB_SUPPORT_EN BIT(13)