| Message ID | 20220305112607.257734-2-linux@fw-web.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add sata nodes to rk356x | expand |
On 05/03/2022 12:26, Frank Wunderlich wrote: > From: Frank Wunderlich <frank-w@public-files.de> > > Create a yaml file for dtbs_check from the old txt binding. > > Signed-off-by: Frank Wunderlich <frank-w@public-files.de> > --- > > v5: > - change subject > - drop brcm,iproc-ahci from standalone enum > - fix reg address in example 2 > - move clocknames next to clocks, regnames to reg > - drop interrupts description > - drop newline from dma-coherent > - drop max-items from ports-implemented > - min2max in child phys > - fix identation for compatible and sata-common > - add additionalProperties=false for subnodes > - pipe for paragraphs and newline after title > - add maximum for ports-implemented (found only 0x1 as its value) > - add phy-names to sata-ports > > v4: > - fix min vs. max > - fix indention of examples > - move up sata-common.yaml > - reorder compatible > - add descriptions/maxitems > - fix compatible-structure > - fix typo in example achi vs. ahci > - add clock-names and reg-names > - fix ns2 errors in separate patch > v3: > - add conversion to sata-series > - fix some errors in dt_binding_check and dtbs_check > - move to unevaluated properties = false > > --- > .../devicetree/bindings/ata/ahci-platform.txt | 79 --------- > .../bindings/ata/ahci-platform.yaml | 163 ++++++++++++++++++ > 2 files changed, 163 insertions(+), 79 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/ata/ahci-platform.txt > create mode 100644 Documentation/devicetree/bindings/ata/ahci-platform.yaml > > diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt > deleted file mode 100644 > index 77091a277642..000000000000 > --- a/Documentation/devicetree/bindings/ata/ahci-platform.txt > +++ /dev/null > @@ -1,79 +0,0 @@ > -* AHCI SATA Controller > - > -SATA nodes are defined to describe on-chip Serial ATA controllers. > -Each SATA controller should have its own node. > - > -It is possible, but not required, to represent each port as a sub-node. > -It allows to enable each port independently when dealing with multiple > -PHYs. > - > -Required properties: > -- compatible : compatible string, one of: > - - "brcm,iproc-ahci" > - - "hisilicon,hisi-ahci" > - - "cavium,octeon-7130-ahci" > - - "ibm,476gtr-ahci" > - - "marvell,armada-380-ahci" > - - "marvell,armada-3700-ahci" > - - "snps,dwc-ahci" > - - "snps,spear-ahci" > - - "generic-ahci" > -- interrupts : <interrupt mapping for SATA IRQ> > -- reg : <registers mapping> > - > -Please note that when using "generic-ahci" you must also specify a SoC specific > -compatible: > - compatible = "manufacturer,soc-model-ahci", "generic-ahci"; > - > -Optional properties: > -- dma-coherent : Present if dma operations are coherent > -- clocks : a list of phandle + clock specifier pairs > -- resets : a list of phandle + reset specifier pairs > -- target-supply : regulator for SATA target power > -- phy-supply : regulator for PHY power > -- phys : reference to the SATA PHY node > -- phy-names : must be "sata-phy" > -- ahci-supply : regulator for AHCI controller > -- ports-implemented : Mask that indicates which ports that the HBA supports > - are available for software to use. Useful if PORTS_IMPL > - is not programmed by the BIOS, which is true with > - some embedded SOC's. > - > -Required properties when using sub-nodes: > -- #address-cells : number of cells to encode an address > -- #size-cells : number of cells representing the size of an address > - > -Sub-nodes required properties: > -- reg : the port number > -And at least one of the following properties: > -- phys : reference to the SATA PHY node > -- target-supply : regulator for SATA target power > - > -Examples: > - sata@ffe08000 { > - compatible = "snps,spear-ahci"; > - reg = <0xffe08000 0x1000>; > - interrupts = <115>; > - }; > - > -With sub-nodes: > - sata@f7e90000 { > - compatible = "marvell,berlin2q-achi", "generic-ahci"; > - reg = <0xe90000 0x1000>; > - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&chip CLKID_SATA>; > - #address-cells = <1>; > - #size-cells = <0>; > - > - sata0: sata-port@0 { > - reg = <0>; > - phys = <&sata_phy 0>; > - target-supply = <®_sata0>; > - }; > - > - sata1: sata-port@1 { > - reg = <1>; > - phys = <&sata_phy 1>; > - target-supply = <®_sata1>;; > - }; > - }; > diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.yaml b/Documentation/devicetree/bindings/ata/ahci-platform.yaml > new file mode 100644 > index 000000000000..fae042539824 > --- /dev/null > +++ b/Documentation/devicetree/bindings/ata/ahci-platform.yaml > @@ -0,0 +1,163 @@ > +# SPDX-License-Identifier: GPL-2.0 > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/ata/ahci-platform.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: AHCI SATA Controller > + > +description: | > + SATA nodes are defined to describe on-chip Serial ATA controllers. > + Each SATA controller should have its own node. > + > + It is possible, but not required, to represent each port as a sub-node. > + It allows to enable each port independently when dealing with multiple > + PHYs. > + > +maintainers: > + - Hans de Goede <hdegoede@redhat.com> > + - Jens Axboe <axboe@kernel.dk> > + > +allOf: > + - $ref: "sata-common.yaml#" > + > +properties: > + compatible: > + oneOf: > + - items: > + - enum: > + - brcm,iproc-ahci > + - marvell,armada-8k-ahci > + - marvell,berlin2q-ahci > + - const: generic-ahci > + - enum: > + - cavium,octeon-7130-ahci > + - hisilicon,hisi-ahci > + - ibm,476gtr-ahci > + - marvell,armada-3700-ahci > + - marvell,armada-380-ahci > + - snps,dwc-ahci > + - snps,spear-ahci > + > + reg: > + maxItems: 1 > + > + reg-names: > + maxItems: 1 > + > + clocks: > + description: > + Clock IDs array as required by the controller. > + minItems: 1 > + maxItems: 3 > + > + clock-names: > + description: > + Names of clocks corresponding to IDs in the clock property. > + minItems: 1 > + maxItems: 3 > + > + interrupts: > + maxItems: 1 > + > + ahci-supply: > + description: > + regulator for AHCI controller > + > + dma-coherent: true > + > + phy-supply: > + description: > + regulator for PHY power > + > + phys: > + description: > + List of all PHYs on this controller > + maxItems: 1 > + > + phy-names: > + description: > + Name specifier for the PHYs > + maxItems: 1 > + > + ports-implemented: > + $ref: '/schemas/types.yaml#/definitions/uint32' > + description: | > + Mask that indicates which ports that the HBA supports > + are available for software to use. Useful if PORTS_IMPL > + is not programmed by the BIOS, which is true with > + some embedded SoCs. > + maximum: 0x1 > + > + resets: > + maxItems: 1 > + > + target-supply: > + description: > + regulator for SATA target power > + > +required: > + - compatible > + - reg > + - interrupts > + > +patternProperties: > + "^sata-port@[0-9a-f]+$": > + type: object > + additionalProperties: false > + description: > + Subnode with configuration of the Ports. > + > + properties: > + reg: > + maxItems: 1 > + > + phys: > + maxItems: 1 > + > + phy-names: > + maxItems: 1 > + > + target-supply: > + description: > + regulator for SATA target power > + > + required: > + - reg > + > + anyOf: > + - required: [ phys ] > + - required: [ target-supply ] > + > +unevaluatedProperties: false > + > +examples: > + - | > + sata@ffe08000 { > + compatible = "snps,spear-ahci"; > + reg = <0xffe08000 0x1000>; > + interrupts = <115>; Thanks for the changes, all look good except now I noticed that indentation of example is unusual. It's not consistent. Starts with four space (correct) but then goes to 7 spaces. Please adjust entire example to use 4 spaces indentation. With that: Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Best regards, Krzysztof
Hi Krzysztof,
have seen some warnings in Robs bot for arm.
imho have fixed them (and the indention you've mentioned already squashed) in my tree [1].
add compatibles used together with generic-ahci
- marvell,berlin2-ahci
- qcom,apq8064-ahci
- qcom,ipq806x-ahci
increase reg-count to 2 (used in omap5-l4.dtsi)
increase clock-count to 5 (used in qcom-apq8064.dtsi)
can i still add you reviewed-by to v6?
[1] https://github.com/frank-w/BPI-R2-4.14/commits/5.17-next-20220225
regards Frank
> Gesendet: Samstag, 05. März 2022 um 18:43 Uhr
> Von: "Krzysztof Kozlowski" <krzysztof.kozlowski@canonical.com>
>
> Thanks for the changes, all look good except now I noticed that
> indentation of example is unusual. It's not consistent. Starts with four
> space (correct) but then goes to 7 spaces. Please adjust entire example
> to use 4 spaces indentation.
>
> With that:
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
On 06/03/2022 10:47, Frank Wunderlich wrote: > Hi Krzysztof, > > have seen some warnings in Robs bot for arm. > > imho have fixed them (and the indention you've mentioned already squashed) in my tree [1]. > > add compatibles used together with generic-ahci > - marvell,berlin2-ahci This is fine, just mention it in commit msg. > - qcom,apq8064-ahci > - qcom,ipq806x-ahci These you need to consult with qcom-sata.txt. This could be a following commit which will integrate qcom-sata.txt and remove it. Either you have binding document for all devices or you create a common part, like for UFS: https://lore.kernel.org/linux-devicetree/20220222145854.358646-1-krzysztof.kozlowski@canonical.com/ https://github.com/krzk/linux/commits/n/dt-bindings-ufs-v2 The choice depends more or less on complexity of bindings, IOW, how big and complicated bindings would be if you combine everything to one YAML. In the case of UFS, the devices differ - by clocks, resets, phys and sometimes supplies. Therefore it easier to have one common shared part and several device bindings. AHCI looks more consistent - except that Qualcomm - so maybe better to have one document. > increase reg-count to 2 (used in omap5-l4.dtsi) > increase clock-count to 5 (used in qcom-apq8064.dtsi) This would need allOf+if. > > can i still add you reviewed-by to v6? Keeping reviewed-by would be fine when adding compatibles and bumping maxItems, but in your case you need to rework these bindings. Either by growing document with several "if:" or by splitting them, so it will be significant change. Skip my review then. > > [1] https://github.com/frank-w/BPI-R2-4.14/commits/5.17-next-20220225 > > regards Frank > > >> Gesendet: Samstag, 05. März 2022 um 18:43 Uhr >> Von: "Krzysztof Kozlowski" <krzysztof.kozlowski@canonical.com> >> >> Thanks for the changes, all look good except now I noticed that >> indentation of example is unusual. It's not consistent. Starts with four >> space (correct) but then goes to 7 spaces. Please adjust entire example >> to use 4 spaces indentation. >> >> With that: >> >> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> > > Best regards, Krzysztof
> Gesendet: Sonntag, 06. März 2022 um 11:27 Uhr > Von: "Krzysztof Kozlowski" <krzysztof.kozlowski@canonical.com> > > add compatibles used together with generic-ahci > > - marvell,berlin2-ahci > > This is fine, just mention it in commit msg. > > > - qcom,apq8064-ahci > > - qcom,ipq806x-ahci > > These you need to consult with qcom-sata.txt. This could be a following > commit which will integrate qcom-sata.txt and remove it. this depends on Robs opinion > Either you have > binding document for all devices or you create a common part, like for UFS: > https://lore.kernel.org/linux-devicetree/20220222145854.358646-1-krzysztof.kozlowski@canonical.com/ > https://github.com/krzk/linux/commits/n/dt-bindings-ufs-v2 > > The choice depends more or less on complexity of bindings, IOW, how big > and complicated bindings would be if you combine everything to one YAML. > > In the case of UFS, the devices differ - by clocks, resets, phys and > sometimes supplies. Therefore it easier to have one common shared part > and several device bindings. > > AHCI looks more consistent - except that Qualcomm - so maybe better to > have one document. > > > increase reg-count to 2 (used in omap5-l4.dtsi) > > increase clock-count to 5 (used in qcom-apq8064.dtsi) > > This would need allOf+if. if i get ok from rob i add only the berlin-compatible and skip the qcom+reg/clock-change in the first applied version. Adding the allOf/if (and making it right) will only delay the sata-binding/dts-change. > > > > can i still add you reviewed-by to v6? > > Keeping reviewed-by would be fine when adding compatibles and bumping > maxItems, but in your case you need to rework these bindings. Either by > growing document with several "if:" or by splitting them, so it will be > significant change. Skip my review then. > > > > > [1] https://github.com/frank-w/BPI-R2-4.14/commits/5.17-next-20220225 regards Frank
On 06/03/2022 11:41, Frank Wunderlich wrote: >> Gesendet: Sonntag, 06. März 2022 um 11:27 Uhr >> Von: "Krzysztof Kozlowski" <krzysztof.kozlowski@canonical.com> >>> add compatibles used together with generic-ahci >>> - marvell,berlin2-ahci >> >> This is fine, just mention it in commit msg. >> >>> - qcom,apq8064-ahci >>> - qcom,ipq806x-ahci >> >> These you need to consult with qcom-sata.txt. This could be a following >> commit which will integrate qcom-sata.txt and remove it. > > this depends on Robs opinion Then maybe precise the question for Rob... > >> Either you have >> binding document for all devices or you create a common part, like for UFS: >> https://lore.kernel.org/linux-devicetree/20220222145854.358646-1-krzysztof.kozlowski@canonical.com/ >> https://github.com/krzk/linux/commits/n/dt-bindings-ufs-v2 >> >> The choice depends more or less on complexity of bindings, IOW, how big >> and complicated bindings would be if you combine everything to one YAML. >> >> In the case of UFS, the devices differ - by clocks, resets, phys and >> sometimes supplies. Therefore it easier to have one common shared part >> and several device bindings. >> >> AHCI looks more consistent - except that Qualcomm - so maybe better to >> have one document. >> >>> increase reg-count to 2 (used in omap5-l4.dtsi) >>> increase clock-count to 5 (used in qcom-apq8064.dtsi) >> >> This would need allOf+if. > > if i get ok from rob i add only the berlin-compatible and skip the qcom+reg/clock-change in the first applied version. Adding the allOf/if (and making it right) will only delay the sata-binding/dts-change. I don't get what is the problem with delaying this patch for the time needed to make the bindings correct? Especially that alternative is to add bindings document which soon will need to be modified, e.g. split into common part. Is there a particular hurry with these bindings conversion? Best regards, Krzysztof
> Gesendet: Sonntag, 06. März 2022 um 12:15 Uhr > Von: "Krzysztof Kozlowski" <krzysztof.kozlowski@canonical.com> > An: "Frank Wunderlich" <frank-w@public-files.de> > Cc: "Frank Wunderlich" <linux@fw-web.de>, devicetree@vger.kernel.org, "Damien Le Moal" <damien.lemoal@opensource.wdc.com>, "Rob Herring" <robh+dt@kernel.org>, "Andrew Lunn" <andrew@lunn.ch>, "Gregory Clement" <gregory.clement@bootlin.com>, "Sebastian Hesselbarth" <sebastian.hesselbarth@gmail.com>, "Russell King" <linux@armlinux.org.uk>, "Heiko Stuebner" <heiko@sntech.de>, "Peter Geis" <pgwipeout@gmail.com>, "Michael Riesch" <michael.riesch@wolfvision.net>, "Hans de Goede" <hdegoede@redhat.com>, "Jens Axboe" <axboe@kernel.dk>, linux-ide@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org > Betreff: Re: Aw: Re: Re: [PATCH v5 1/5] dt-bindings: ata: ahci-platform: Convert DT bindings to yaml > > On 06/03/2022 11:41, Frank Wunderlich wrote: > >> Gesendet: Sonntag, 06. März 2022 um 11:27 Uhr > >> Von: "Krzysztof Kozlowski" <krzysztof.kozlowski@canonical.com> > >>> add compatibles used together with generic-ahci > >>> - marvell,berlin2-ahci > >> > >> This is fine, just mention it in commit msg. > >> > >>> - qcom,apq8064-ahci > >>> - qcom,ipq806x-ahci > >> > >> These you need to consult with qcom-sata.txt. This could be a following > >> commit which will integrate qcom-sata.txt and remove it. > > > > this depends on Robs opinion > > Then maybe precise the question for Rob... do i need to fix the errors for qcom-compatibles/reg-count/clock-count (reported by your bot) *now*? or is binding well enough with adding berlin-compatible and fixing the indentation error in example? for the marvell anyof issue and the spear13xx i have a patch in my tree which i include in v6 > > > >> Either you have > >> binding document for all devices or you create a common part, like for UFS: > >> https://lore.kernel.org/linux-devicetree/20220222145854.358646-1-krzysztof.kozlowski@canonical.com/ > >> https://github.com/krzk/linux/commits/n/dt-bindings-ufs-v2 > >> > >> The choice depends more or less on complexity of bindings, IOW, how big > >> and complicated bindings would be if you combine everything to one YAML. > >> > >> In the case of UFS, the devices differ - by clocks, resets, phys and > >> sometimes supplies. Therefore it easier to have one common shared part > >> and several device bindings. > >> > >> AHCI looks more consistent - except that Qualcomm - so maybe better to > >> have one document. > >> > >>> increase reg-count to 2 (used in omap5-l4.dtsi) > >>> increase clock-count to 5 (used in qcom-apq8064.dtsi) > >> > >> This would need allOf+if. > > > > if i get ok from rob i add only the berlin-compatible and skip the qcom+reg/clock-change in the first applied version. Adding the allOf/if (and making it right) will only delay the sata-binding/dts-change. > > I don't get what is the problem with delaying this patch for the time > needed to make the bindings correct? Especially that alternative is to > add bindings document which soon will need to be modified, e.g. split > into common part. Is there a particular hurry with these bindings > conversion? i see it as requirement for last part "arm64: dts: rockchip: Add sata nodes to rk356x" if this can applied without the bindings conversion there is nothing to hurry :) regards Frank
On 06/03/2022 12:46, Frank Wunderlich wrote: > > i see it as requirement for last part > > "arm64: dts: rockchip: Add sata nodes to rk356x" > > if this can applied without the bindings conversion there is nothing to hurry :) This actually depends more on Heiko, whether he is willing to take DTS change even though the compatible was not yet merged. There is no strict dependency here, so DTS change could go now... Best regards, Krzysztof
On Sun, Mar 06, 2022 at 12:15:39PM +0100, Krzysztof Kozlowski wrote: > On 06/03/2022 11:41, Frank Wunderlich wrote: > >> Gesendet: Sonntag, 06. März 2022 um 11:27 Uhr > >> Von: "Krzysztof Kozlowski" <krzysztof.kozlowski@canonical.com> > >>> add compatibles used together with generic-ahci > >>> - marvell,berlin2-ahci > >> > >> This is fine, just mention it in commit msg. > >> > >>> - qcom,apq8064-ahci > >>> - qcom,ipq806x-ahci > >> > >> These you need to consult with qcom-sata.txt. This could be a following > >> commit which will integrate qcom-sata.txt and remove it. > > > > this depends on Robs opinion > > Then maybe precise the question for Rob... I would leave qcom separate, but the warnings should be fixed. For that you need a custom 'select' schema that lists everything but 'generic-ahci'. Adding the berlin compatible looks right. > >> Either you have > >> binding document for all devices or you create a common part, like for UFS: > >> https://lore.kernel.org/linux-devicetree/20220222145854.358646-1-krzysztof.kozlowski@canonical.com/ > >> https://github.com/krzk/linux/commits/n/dt-bindings-ufs-v2 > >> > >> The choice depends more or less on complexity of bindings, IOW, how big > >> and complicated bindings would be if you combine everything to one YAML. > >> > >> In the case of UFS, the devices differ - by clocks, resets, phys and > >> sometimes supplies. Therefore it easier to have one common shared part > >> and several device bindings. > >> > >> AHCI looks more consistent - except that Qualcomm - so maybe better to > >> have one document. > >> > >>> increase reg-count to 2 (used in omap5-l4.dtsi) > >>> increase clock-count to 5 (used in qcom-apq8064.dtsi) > >> > >> This would need allOf+if. > > > > if i get ok from rob i add only the berlin-compatible and skip the > > qcom+reg/clock-change in the first applied version. Adding the > > allOf/if (and making it right) will only delay the sata-binding/dts-change. > > I don't get what is the problem with delaying this patch for the time > needed to make the bindings correct? Especially that alternative is to > add bindings document which soon will need to be modified, e.g. split > into common part. Is there a particular hurry with these bindings > conversion? Qcom doesn't use sata-port nodes, so I don't think there is anything to share. And if it did, that's already in sata-common.yaml. Rob
diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt deleted file mode 100644 index 77091a277642..000000000000 --- a/Documentation/devicetree/bindings/ata/ahci-platform.txt +++ /dev/null @@ -1,79 +0,0 @@ -* AHCI SATA Controller - -SATA nodes are defined to describe on-chip Serial ATA controllers. -Each SATA controller should have its own node. - -It is possible, but not required, to represent each port as a sub-node. -It allows to enable each port independently when dealing with multiple -PHYs. - -Required properties: -- compatible : compatible string, one of: - - "brcm,iproc-ahci" - - "hisilicon,hisi-ahci" - - "cavium,octeon-7130-ahci" - - "ibm,476gtr-ahci" - - "marvell,armada-380-ahci" - - "marvell,armada-3700-ahci" - - "snps,dwc-ahci" - - "snps,spear-ahci" - - "generic-ahci" -- interrupts : <interrupt mapping for SATA IRQ> -- reg : <registers mapping> - -Please note that when using "generic-ahci" you must also specify a SoC specific -compatible: - compatible = "manufacturer,soc-model-ahci", "generic-ahci"; - -Optional properties: -- dma-coherent : Present if dma operations are coherent -- clocks : a list of phandle + clock specifier pairs -- resets : a list of phandle + reset specifier pairs -- target-supply : regulator for SATA target power -- phy-supply : regulator for PHY power -- phys : reference to the SATA PHY node -- phy-names : must be "sata-phy" -- ahci-supply : regulator for AHCI controller -- ports-implemented : Mask that indicates which ports that the HBA supports - are available for software to use. Useful if PORTS_IMPL - is not programmed by the BIOS, which is true with - some embedded SOC's. - -Required properties when using sub-nodes: -- #address-cells : number of cells to encode an address -- #size-cells : number of cells representing the size of an address - -Sub-nodes required properties: -- reg : the port number -And at least one of the following properties: -- phys : reference to the SATA PHY node -- target-supply : regulator for SATA target power - -Examples: - sata@ffe08000 { - compatible = "snps,spear-ahci"; - reg = <0xffe08000 0x1000>; - interrupts = <115>; - }; - -With sub-nodes: - sata@f7e90000 { - compatible = "marvell,berlin2q-achi", "generic-ahci"; - reg = <0xe90000 0x1000>; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&chip CLKID_SATA>; - #address-cells = <1>; - #size-cells = <0>; - - sata0: sata-port@0 { - reg = <0>; - phys = <&sata_phy 0>; - target-supply = <®_sata0>; - }; - - sata1: sata-port@1 { - reg = <1>; - phys = <&sata_phy 1>; - target-supply = <®_sata1>;; - }; - }; diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.yaml b/Documentation/devicetree/bindings/ata/ahci-platform.yaml new file mode 100644 index 000000000000..fae042539824 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/ahci-platform.yaml @@ -0,0 +1,163 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/ahci-platform.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AHCI SATA Controller + +description: | + SATA nodes are defined to describe on-chip Serial ATA controllers. + Each SATA controller should have its own node. + + It is possible, but not required, to represent each port as a sub-node. + It allows to enable each port independently when dealing with multiple + PHYs. + +maintainers: + - Hans de Goede <hdegoede@redhat.com> + - Jens Axboe <axboe@kernel.dk> + +allOf: + - $ref: "sata-common.yaml#" + +properties: + compatible: + oneOf: + - items: + - enum: + - brcm,iproc-ahci + - marvell,armada-8k-ahci + - marvell,berlin2q-ahci + - const: generic-ahci + - enum: + - cavium,octeon-7130-ahci + - hisilicon,hisi-ahci + - ibm,476gtr-ahci + - marvell,armada-3700-ahci + - marvell,armada-380-ahci + - snps,dwc-ahci + - snps,spear-ahci + + reg: + maxItems: 1 + + reg-names: + maxItems: 1 + + clocks: + description: + Clock IDs array as required by the controller. + minItems: 1 + maxItems: 3 + + clock-names: + description: + Names of clocks corresponding to IDs in the clock property. + minItems: 1 + maxItems: 3 + + interrupts: + maxItems: 1 + + ahci-supply: + description: + regulator for AHCI controller + + dma-coherent: true + + phy-supply: + description: + regulator for PHY power + + phys: + description: + List of all PHYs on this controller + maxItems: 1 + + phy-names: + description: + Name specifier for the PHYs + maxItems: 1 + + ports-implemented: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: | + Mask that indicates which ports that the HBA supports + are available for software to use. Useful if PORTS_IMPL + is not programmed by the BIOS, which is true with + some embedded SoCs. + maximum: 0x1 + + resets: + maxItems: 1 + + target-supply: + description: + regulator for SATA target power + +required: + - compatible + - reg + - interrupts + +patternProperties: + "^sata-port@[0-9a-f]+$": + type: object + additionalProperties: false + description: + Subnode with configuration of the Ports. + + properties: + reg: + maxItems: 1 + + phys: + maxItems: 1 + + phy-names: + maxItems: 1 + + target-supply: + description: + regulator for SATA target power + + required: + - reg + + anyOf: + - required: [ phys ] + - required: [ target-supply ] + +unevaluatedProperties: false + +examples: + - | + sata@ffe08000 { + compatible = "snps,spear-ahci"; + reg = <0xffe08000 0x1000>; + interrupts = <115>; + }; + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/berlin2q.h> + sata@f7e90000 { + compatible = "marvell,berlin2q-ahci", "generic-ahci"; + reg = <0xf7e90000 0x1000>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&chip CLKID_SATA>; + #address-cells = <1>; + #size-cells = <0>; + + sata0: sata-port@0 { + reg = <0>; + phys = <&sata_phy 0>; + target-supply = <®_sata0>; + }; + + sata1: sata-port@1 { + reg = <1>; + phys = <&sata_phy 1>; + target-supply = <®_sata1>; + }; + };