diff mbox series

pinctrl: aspeed: Add FWQSPI pinmux

Message ID 20220308003136.3930466-1-quic_jaehyoo@quicinc.com (mailing list archive)
State New, archived
Headers show
Series pinctrl: aspeed: Add FWQSPI pinmux | expand

Commit Message

Jae Hyun Yoo March 8, 2022, 12:31 a.m. UTC 
From: Johnny Huang <johnny_huang@aspeedtech.com>

AST2600 FW SPI quad mode only need to set AE12 and AF12, no need
to set Y1~Y4. FW SPI cs, clk, mosi and miso pins are dedicated.

Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com>
---
 drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

Comments

Andrew Jeffery March 8, 2022, 12:41 a.m. UTC | #1 
On Tue, 8 Mar 2022, at 11:01, Jae Hyun Yoo wrote:
> From: Johnny Huang <johnny_huang@aspeedtech.com>
>
> AST2600 FW SPI quad mode only need to set AE12 and AF12, no need
> to set Y1~Y4. FW SPI cs, clk, mosi and miso pins are dedicated.

They're not dedicated according to the datasheet?

Can you please look at this patch?

https://lore.kernel.org/all/20220304011010.974863-1-joel@jms.id.au/

Cheers,

Andrew
Jae Hyun Yoo March 8, 2022, 12:46 a.m. UTC | #2 
Hi Andrew,

On 3/7/2022 4:41 PM, Andrew Jeffery wrote:
> 
> 
> On Tue, 8 Mar 2022, at 11:01, Jae Hyun Yoo wrote:
>> From: Johnny Huang <johnny_huang@aspeedtech.com>
>>
>> AST2600 FW SPI quad mode only need to set AE12 and AF12, no need
>> to set Y1~Y4. FW SPI cs, clk, mosi and miso pins are dedicated.
> 
> They're not dedicated according to the datasheet?
> 
> Can you please look at this patch?
> 
> https://lore.kernel.org/all/20220304011010.974863-1-joel@jms.id.au/

Sorry. Please ignore this patch.
I mistakenly sent this patch while making a patch series.

Please check this patch series instead.
https://lore.kernel.org/linux-arm-kernel/20220308003745.3930607-1-quic_jaehyoo@quicinc.com/T/#t

Thanks,

Jae

> Cheers,
> 
> Andrew
>
Andrew Jeffery March 8, 2022, 1:02 a.m. UTC | #3 
On Tue, 8 Mar 2022, at 11:16, Jae Hyun Yoo wrote:
> Hi Andrew,
>
> On 3/7/2022 4:41 PM, Andrew Jeffery wrote:
>> 
>> 
>> On Tue, 8 Mar 2022, at 11:01, Jae Hyun Yoo wrote:
>>> From: Johnny Huang <johnny_huang@aspeedtech.com>
>>>
>>> AST2600 FW SPI quad mode only need to set AE12 and AF12, no need
>>> to set Y1~Y4. FW SPI cs, clk, mosi and miso pins are dedicated.
>> 
>> They're not dedicated according to the datasheet?
>> 
>> Can you please look at this patch?
>> 
>> https://lore.kernel.org/all/20220304011010.974863-1-joel@jms.id.au/
>
> Sorry. Please ignore this patch.
> I mistakenly sent this patch while making a patch series.
>
> Please check this patch series instead.
> https://lore.kernel.org/linux-arm-kernel/20220308003745.3930607-1-quic_jaehyoo@quicinc.com/T/#t

No worries, I'll take a look though it might be a couple of days due to chasing some other issues.

Andrew
Jae Hyun Yoo March 8, 2022, 1:04 a.m. UTC | #4 
On 3/7/2022 5:02 PM, Andrew Jeffery wrote:
> 
> 
> On Tue, 8 Mar 2022, at 11:16, Jae Hyun Yoo wrote:
>> Hi Andrew,
>>
>> On 3/7/2022 4:41 PM, Andrew Jeffery wrote:
>>>
>>>
>>> On Tue, 8 Mar 2022, at 11:01, Jae Hyun Yoo wrote:
>>>> From: Johnny Huang <johnny_huang@aspeedtech.com>
>>>>
>>>> AST2600 FW SPI quad mode only need to set AE12 and AF12, no need
>>>> to set Y1~Y4. FW SPI cs, clk, mosi and miso pins are dedicated.
>>>
>>> They're not dedicated according to the datasheet?
>>>
>>> Can you please look at this patch?
>>>
>>> https://lore.kernel.org/all/20220304011010.974863-1-joel@jms.id.au/
>>
>> Sorry. Please ignore this patch.
>> I mistakenly sent this patch while making a patch series.
>>
>> Please check this patch series instead.
>> https://lore.kernel.org/linux-arm-kernel/20220308003745.3930607-1-quic_jaehyoo@quicinc.com/T/#t
> 
> No worries, I'll take a look though it might be a couple of days due to chasing some other issues.

Thanks a lot, Andrew!

-Jae
diff mbox series

Patch

diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
index 54064714d73f..80838dc54b3a 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
@@ -1236,12 +1236,17 @@  FUNC_GROUP_DECL(SALT8, AA12);
 FUNC_GROUP_DECL(WDTRST4, AA12);
 
 #define AE12 196
+SIG_EXPR_LIST_DECL_SESG(AE12, FWSPIQ2, FWQSPI, SIG_DESC_SET(SCU438, 4));
 SIG_EXPR_LIST_DECL_SESG(AE12, GPIOY4, GPIOY4);
-PIN_DECL_(AE12, SIG_EXPR_LIST_PTR(AE12, GPIOY4));
+PIN_DECL_(AE12, SIG_EXPR_LIST_PTR(AE12, FWSPIQ2),
+	  SIG_EXPR_LIST_PTR(AE12, GPIOY4));
 
 #define AF12 197
+SIG_EXPR_LIST_DECL_SESG(AF12, FWSPIQ3, FWQSPI, SIG_DESC_SET(SCU438, 5));
 SIG_EXPR_LIST_DECL_SESG(AF12, GPIOY5, GPIOY5);
-PIN_DECL_(AF12, SIG_EXPR_LIST_PTR(AF12, GPIOY5));
+PIN_DECL_(AF12, SIG_EXPR_LIST_PTR(AF12, FWSPIQ3),
+	  SIG_EXPR_LIST_PTR(AF12, GPIOY5));
+FUNC_GROUP_DECL(FWQSPI, AE12, AF12);
 
 #define AC12 198
 SSSF_PIN_DECL(AC12, GPIOY6, FWSPIABR, SIG_DESC_SET(SCU438, 6));
@@ -1911,6 +1916,7 @@  static const struct aspeed_pin_group aspeed_g6_groups[] = {
 	ASPEED_PINCTRL_GROUP(FSI2),
 	ASPEED_PINCTRL_GROUP(FWSPIABR),
 	ASPEED_PINCTRL_GROUP(FWSPID),
+	ASPEED_PINCTRL_GROUP(FWQSPI),
 	ASPEED_PINCTRL_GROUP(FWSPIWP),
 	ASPEED_PINCTRL_GROUP(GPIT0),
 	ASPEED_PINCTRL_GROUP(GPIT1),
@@ -2152,6 +2158,7 @@  static const struct aspeed_pin_function aspeed_g6_functions[] = {
 	ASPEED_PINCTRL_FUNC(FSI2),
 	ASPEED_PINCTRL_FUNC(FWSPIABR),
 	ASPEED_PINCTRL_FUNC(FWSPID),
+	ASPEED_PINCTRL_FUNC(FWQSPI),
 	ASPEED_PINCTRL_FUNC(FWSPIWP),
 	ASPEED_PINCTRL_FUNC(GPIT0),
 	ASPEED_PINCTRL_FUNC(GPIT1),