| Message ID | 20220307021208.2406741-1-colin.foster@in-advantage.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | add support for VSC7512 control over SPI | expand |
On Sun, Mar 06, 2022 at 06:11:55PM -0800, Colin Foster wrote: > The patch set in general is to add support for the VSC7512, and > eventually the VSC7511, VSC7513 and VSC7514 devices controlled over > SPI. The driver is believed to be fully functional for the internal > phy ports (0-3) on the VSC7512. It is not yet functional for SGMII, > QSGMII, and SerDes ports. > > I have mentioned previously: > The hardware setup I'm using for development is a beaglebone black, with > jumpers from SPI0 to the microchip VSC7512 dev board. The microchip dev > board has been modified to not boot from flash, but wait for SPI. An > ethernet cable is connected from the beaglebone ethernet to port 0 of > the dev board. > > The relevant sections of the device tree I'm using for the VSC7512 is > below. Notably the SGPIO LEDs follow link status and speed from network > triggers. > > In order to make this work, I have modified the cpsw driver, and now the > cpsw_new driver, to allow for frames over 1500 bytes. Otherwise the > tagging protocol will not work between the beaglebone and the VSC7512. I > plan to eventually try to get those changes in mainline, but I don't > want to get distracted from my initial goal. I also had to change > bonecommon.dtsi to avoid using VLAN 0. > > > Of note: The Felix driver had the ability to register the internal MDIO > bus. I am no longer using that in the switch driver, it is now an > additional sub-device under the MFD. > > I also made use of IORESOURCE_REG, which removed the "device_is_mfd" > requirement. > > > / { > vscleds { > compatible = "gpio-leds"; > vscled@0 { > label = "port0led"; > gpios = <&sgpio_out1 0 0 GPIO_ACTIVE_LOW>; > default-state = "off"; > linux,default-trigger = "ocelot-miim0.2.auto-mii:00:link"; > }; > vscled@1 { > label = "port0led1"; > gpios = <&sgpio_out1 0 1 GPIO_ACTIVE_LOW>; > default-state = "off"; > linux,default-trigger = "ocelot-miim0.2.auto-mii:00:1Gbps"; > }; > [ ... ] > vscled@71 { > label = "port7led1"; > gpios = <&sgpio_out1 7 1 GPIO_ACTIVE_LOW>; > default-state = "off"; > linux,default-trigger = "ocelot-miim1-mii:07:1Gbps"; > }; > }; > }; > > &spi0 { > #address-cells = <1>; > #size-cells = <0>; > status = "okay"; > > ocelot-chip@0 { > compatible = "mscc,vsc7512_mfd_spi"; > spi-max-frequency = <2500000>; > reg = <0>; > > ethernet-switch@0 { I'm not exactly clear on what exactly does the bus address (@0) represent here and in other (but not all) sub-nodes. dtc probably warns that there shouldn't be any unit address, since #address-cells and #size-cells are both 0 for ocelot-chip@0. > compatible = "mscc,vsc7512-ext-switch"; > ports { > #address-cells = <1>; > #size-cells = <0>; > > port@0 { > reg = <0>; > label = "cpu"; > status = "okay"; > ethernet = <&mac_sw>; > phy-handle = <&sw_phy0>; > phy-mode = "internal"; > }; > > port@1 { > reg = <1>; > label = "swp1"; > status = "okay"; > phy-handle = <&sw_phy1>; > phy-mode = "internal"; > }; > }; > }; > > mdio0: mdio0@0 { > compatible = "mscc,ocelot-miim"; > #address-cells = <1>; > #size-cells = <0>; > > sw_phy0: ethernet-phy@0 { > reg = <0x0>; > }; > > sw_phy1: ethernet-phy@1 { > reg = <0x1>; > }; > > sw_phy2: ethernet-phy@2 { > reg = <0x2>; > }; > > sw_phy3: ethernet-phy@3 { > reg = <0x3>; > }; > }; > > mdio1: mdio1@1 { > compatible = "mscc,ocelot-miim"; > pinctrl-names = "default"; > pinctrl-0 = <&miim1>; > #address-cells = <1>; > #size-cells = <0>; > > sw_phy4: ethernet-phy@4 { > reg = <0x4>; > }; > > sw_phy5: ethernet-phy@5 { > reg = <0x5>; > }; > > sw_phy6: ethernet-phy@6 { > reg = <0x6>; > }; > > sw_phy7: ethernet-phy@7 { > reg = <0x7>; > }; > > }; > > gpio: pinctrl@0 { > compatible = "mscc,ocelot-pinctrl"; > gpio-controller; > #gpio_cells = <2>; > gpio-ranges = <&gpio 0 0 22>; > > led_shift_reg_pins: led-shift-reg-pins { > pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3"; > function = "sg0"; > }; > > miim1: miim1 { > pins = "GPIO_14", "GPIO_15"; > function = "miim"; > }; > }; > > sgpio: sgpio { > compatible = "mscc,ocelot-sgpio"; > #address-cells = <1>; > #size-cells = <0>; > bus-frequency=<12500000>; > clocks = <&ocelot_clock>; > microchip,sgpio-port-ranges = <0 15>; > pinctrl-names = "default"; > pinctrl-0 = <&led_shift_reg_pins>; > > sgpio_in0: sgpio@0 { > compatible = "microchip,sparx5-sgpio-bank"; > reg = <0>; > gpio-controller; > #gpio-cells = <3>; > ngpios = <64>; > }; > > sgpio_out1: sgpio@1 { > compatible = "microchip,sparx5-sgpio-bank"; > reg = <1>; > gpio-controller; > #gpio-cells = <3>; > ngpios = <64>; > }; > }; > > hsio: syscon { > compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd"; > > serdes: serdes { > compatible = "mscc,vsc7514-serdes"; > #phy-cells = <2>; > }; > }; > }; > }; The switch-related portion of this patch set looks good enough to me. I'll let somebody else with more knowledge provide feedback on the mfd/pinctrl/gpio/phylink/led integration aspects.
On Tue, Mar 08, 2022 at 02:39:57PM +0000, Vladimir Oltean wrote: > On Sun, Mar 06, 2022 at 06:11:55PM -0800, Colin Foster wrote: > > The patch set in general is to add support for the VSC7512, and > > eventually the VSC7511, VSC7513 and VSC7514 devices controlled over > > SPI. The driver is believed to be fully functional for the internal > > phy ports (0-3) on the VSC7512. It is not yet functional for SGMII, > > QSGMII, and SerDes ports. > > > > I have mentioned previously: > > The hardware setup I'm using for development is a beaglebone black, with > > jumpers from SPI0 to the microchip VSC7512 dev board. The microchip dev > > board has been modified to not boot from flash, but wait for SPI. An > > ethernet cable is connected from the beaglebone ethernet to port 0 of > > the dev board. > > > > The relevant sections of the device tree I'm using for the VSC7512 is > > below. Notably the SGPIO LEDs follow link status and speed from network > > triggers. > > > > In order to make this work, I have modified the cpsw driver, and now the > > cpsw_new driver, to allow for frames over 1500 bytes. Otherwise the > > tagging protocol will not work between the beaglebone and the VSC7512. I > > plan to eventually try to get those changes in mainline, but I don't > > want to get distracted from my initial goal. I also had to change > > bonecommon.dtsi to avoid using VLAN 0. > > > > > > Of note: The Felix driver had the ability to register the internal MDIO > > bus. I am no longer using that in the switch driver, it is now an > > additional sub-device under the MFD. > > > > I also made use of IORESOURCE_REG, which removed the "device_is_mfd" > > requirement. > > > > > > / { > > vscleds { > > compatible = "gpio-leds"; > > vscled@0 { > > label = "port0led"; > > gpios = <&sgpio_out1 0 0 GPIO_ACTIVE_LOW>; > > default-state = "off"; > > linux,default-trigger = "ocelot-miim0.2.auto-mii:00:link"; > > }; > > vscled@1 { > > label = "port0led1"; > > gpios = <&sgpio_out1 0 1 GPIO_ACTIVE_LOW>; > > default-state = "off"; > > linux,default-trigger = "ocelot-miim0.2.auto-mii:00:1Gbps"; > > }; > > [ ... ] > > vscled@71 { > > label = "port7led1"; > > gpios = <&sgpio_out1 7 1 GPIO_ACTIVE_LOW>; > > default-state = "off"; > > linux,default-trigger = "ocelot-miim1-mii:07:1Gbps"; > > }; > > }; > > }; > > > > &spi0 { > > #address-cells = <1>; > > #size-cells = <0>; > > status = "okay"; > > > > ocelot-chip@0 { > > compatible = "mscc,vsc7512_mfd_spi"; > > spi-max-frequency = <2500000>; > > reg = <0>; > > > > ethernet-switch@0 { > > I'm not exactly clear on what exactly does the bus address (@0) > represent here and in other (but not all) sub-nodes. > dtc probably warns that there shouldn't be any unit address, since > #address-cells and #size-cells are both 0 for ocelot-chip@0. They most likely shouldn't be there. There are some warnings (make W=1 ...) but they're hidden inside all sorts of warnings from am33*.dtsi warnings. I should have been looking for those. You're right. A lot of "has a unit name, but no reg or ranges property" Removing the @s and giving them all unique names resolves these warnings. > > > compatible = "mscc,vsc7512-ext-switch"; > > ports { > > #address-cells = <1>; > > #size-cells = <0>; > > > > port@0 { > > reg = <0>; > > label = "cpu"; > > status = "okay"; > > ethernet = <&mac_sw>; > > phy-handle = <&sw_phy0>; > > phy-mode = "internal"; > > }; > > > > port@1 { > > reg = <1>; > > label = "swp1"; > > status = "okay"; > > phy-handle = <&sw_phy1>; > > phy-mode = "internal"; > > }; > > }; > > }; > > > > mdio0: mdio0@0 { > > compatible = "mscc,ocelot-miim"; > > #address-cells = <1>; > > #size-cells = <0>; > > > > sw_phy0: ethernet-phy@0 { > > reg = <0x0>; > > }; > > > > sw_phy1: ethernet-phy@1 { > > reg = <0x1>; > > }; > > > > sw_phy2: ethernet-phy@2 { > > reg = <0x2>; > > }; > > > > sw_phy3: ethernet-phy@3 { > > reg = <0x3>; > > }; > > }; > > > > mdio1: mdio1@1 { > > compatible = "mscc,ocelot-miim"; > > pinctrl-names = "default"; > > pinctrl-0 = <&miim1>; > > #address-cells = <1>; > > #size-cells = <0>; > > > > sw_phy4: ethernet-phy@4 { > > reg = <0x4>; > > }; > > > > sw_phy5: ethernet-phy@5 { > > reg = <0x5>; > > }; > > > > sw_phy6: ethernet-phy@6 { > > reg = <0x6>; > > }; > > > > sw_phy7: ethernet-phy@7 { > > reg = <0x7>; > > }; > > > > }; > > > > gpio: pinctrl@0 { > > compatible = "mscc,ocelot-pinctrl"; > > gpio-controller; > > #gpio_cells = <2>; > > gpio-ranges = <&gpio 0 0 22>; > > > > led_shift_reg_pins: led-shift-reg-pins { > > pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3"; > > function = "sg0"; > > }; > > > > miim1: miim1 { > > pins = "GPIO_14", "GPIO_15"; > > function = "miim"; > > }; > > }; > > > > sgpio: sgpio { > > compatible = "mscc,ocelot-sgpio"; > > #address-cells = <1>; > > #size-cells = <0>; > > bus-frequency=<12500000>; > > clocks = <&ocelot_clock>; > > microchip,sgpio-port-ranges = <0 15>; > > pinctrl-names = "default"; > > pinctrl-0 = <&led_shift_reg_pins>; > > > > sgpio_in0: sgpio@0 { > > compatible = "microchip,sparx5-sgpio-bank"; > > reg = <0>; > > gpio-controller; > > #gpio-cells = <3>; > > ngpios = <64>; > > }; > > > > sgpio_out1: sgpio@1 { > > compatible = "microchip,sparx5-sgpio-bank"; > > reg = <1>; > > gpio-controller; > > #gpio-cells = <3>; > > ngpios = <64>; > > }; > > }; > > > > hsio: syscon { > > compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd"; > > > > serdes: serdes { > > compatible = "mscc,vsc7514-serdes"; > > #phy-cells = <2>; > > }; > > }; > > }; > > }; > > The switch-related portion of this patch set looks good enough to me. > I'll let somebody else with more knowledge provide feedback on the > mfd/pinctrl/gpio/phylink/led integration aspects. Thanks for looking. As I mentioned - I don't have any intention to make a .dts/.dtsi for this rather obscure dev environment. It seems like it wouldn't be useful. But the feedback has really helped keep me on track, and hopefully avoiding scenarios where two wrongs make a right.
The patch set in general is to add support for the VSC7512, and eventually the VSC7511, VSC7513 and VSC7514 devices controlled over SPI. The driver is believed to be fully functional for the internal phy ports (0-3) on the VSC7512. It is not yet functional for SGMII, QSGMII, and SerDes ports. I have mentioned previously: The hardware setup I'm using for development is a beaglebone black, with jumpers from SPI0 to the microchip VSC7512 dev board. The microchip dev board has been modified to not boot from flash, but wait for SPI. An ethernet cable is connected from the beaglebone ethernet to port 0 of the dev board. The relevant sections of the device tree I'm using for the VSC7512 is below. Notably the SGPIO LEDs follow link status and speed from network triggers. In order to make this work, I have modified the cpsw driver, and now the cpsw_new driver, to allow for frames over 1500 bytes. Otherwise the tagging protocol will not work between the beaglebone and the VSC7512. I plan to eventually try to get those changes in mainline, but I don't want to get distracted from my initial goal. I also had to change bonecommon.dtsi to avoid using VLAN 0. Of note: The Felix driver had the ability to register the internal MDIO bus. I am no longer using that in the switch driver, it is now an additional sub-device under the MFD. I also made use of IORESOURCE_REG, which removed the "device_is_mfd" requirement. / { vscleds { compatible = "gpio-leds"; vscled@0 { label = "port0led"; gpios = <&sgpio_out1 0 0 GPIO_ACTIVE_LOW>; default-state = "off"; linux,default-trigger = "ocelot-miim0.2.auto-mii:00:link"; }; vscled@1 { label = "port0led1"; gpios = <&sgpio_out1 0 1 GPIO_ACTIVE_LOW>; default-state = "off"; linux,default-trigger = "ocelot-miim0.2.auto-mii:00:1Gbps"; }; [ ... ] vscled@71 { label = "port7led1"; gpios = <&sgpio_out1 7 1 GPIO_ACTIVE_LOW>; default-state = "off"; linux,default-trigger = "ocelot-miim1-mii:07:1Gbps"; }; }; }; &spi0 { #address-cells = <1>; #size-cells = <0>; status = "okay"; ocelot-chip@0 { compatible = "mscc,vsc7512_mfd_spi"; spi-max-frequency = <2500000>; reg = <0>; ethernet-switch@0 { compatible = "mscc,vsc7512-ext-switch"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; label = "cpu"; status = "okay"; ethernet = <&mac_sw>; phy-handle = <&sw_phy0>; phy-mode = "internal"; }; port@1 { reg = <1>; label = "swp1"; status = "okay"; phy-handle = <&sw_phy1>; phy-mode = "internal"; }; }; }; mdio0: mdio0@0 { compatible = "mscc,ocelot-miim"; #address-cells = <1>; #size-cells = <0>; sw_phy0: ethernet-phy@0 { reg = <0x0>; }; sw_phy1: ethernet-phy@1 { reg = <0x1>; }; sw_phy2: ethernet-phy@2 { reg = <0x2>; }; sw_phy3: ethernet-phy@3 { reg = <0x3>; }; }; mdio1: mdio1@1 { compatible = "mscc,ocelot-miim"; pinctrl-names = "default"; pinctrl-0 = <&miim1>; #address-cells = <1>; #size-cells = <0>; sw_phy4: ethernet-phy@4 { reg = <0x4>; }; sw_phy5: ethernet-phy@5 { reg = <0x5>; }; sw_phy6: ethernet-phy@6 { reg = <0x6>; }; sw_phy7: ethernet-phy@7 { reg = <0x7>; }; }; gpio: pinctrl@0 { compatible = "mscc,ocelot-pinctrl"; gpio-controller; #gpio_cells = <2>; gpio-ranges = <&gpio 0 0 22>; led_shift_reg_pins: led-shift-reg-pins { pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3"; function = "sg0"; }; miim1: miim1 { pins = "GPIO_14", "GPIO_15"; function = "miim"; }; }; sgpio: sgpio { compatible = "mscc,ocelot-sgpio"; #address-cells = <1>; #size-cells = <0>; bus-frequency=<12500000>; clocks = <&ocelot_clock>; microchip,sgpio-port-ranges = <0 15>; pinctrl-names = "default"; pinctrl-0 = <&led_shift_reg_pins>; sgpio_in0: sgpio@0 { compatible = "microchip,sparx5-sgpio-bank"; reg = <0>; gpio-controller; #gpio-cells = <3>; ngpios = <64>; }; sgpio_out1: sgpio@1 { compatible = "microchip,sparx5-sgpio-bank"; reg = <1>; gpio-controller; #gpio-cells = <3>; ngpios = <64>; }; }; hsio: syscon { compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd"; serdes: serdes { compatible = "mscc,vsc7514-serdes"; #phy-cells = <2>; }; }; }; }; RFC history: v1 (accidentally named vN) * Initial architecture. Not functional * General concepts laid out v2 * Near functional. No CPU port communication, but control over all external ports * Cleaned up regmap implementation from v1 v3 * Functional * Shared MDIO transactions routed through mdio-mscc-miim * CPU / NPI port enabled by way of vsc7512_enable_npi_port / felix->info->enable_npi_port * NPI port tagging functional - Requires a CPU port driver that supports frames of 1520 bytes. Verified with a patch to the cpsw driver v4 * Functional * Device tree fixes * Add hooks for pinctrl-ocelot - some functionality by way of sysfs * Add hooks for pinctrl-microsemi-sgpio - not yet fully functional * Remove lynx_pcs interface for a generic phylink_pcs. The goal here is to have an ocelot_pcs that will work for each configuration of every port. v5 * Restructured to MFD * Several commits were split out, submitted, and accepted * pinctrl-ocelot believed to be fully functional (requires commits from the linux-pinctrl tree) * External MDIO bus believed to be fully functional v6 * Applied several suggestions from the last RFC from Lee Jones. I hope I didn't miss anything. * Clean up MFD core - SPI interaction. They no longer use callbacks. * regmaps get registered to the child device, and don't attempt to get shared. It seems if a regmap is to be shared, that should be solved with syscon, not dev or mfd. v7 * Applied as much as I could from Lee and Vladimir's suggestions. As always, the feedback is greatly appreciated! * Remove "ocelot_spi" container complication * Move internal MDIO bus from ocelot_ext to MFD, with a devicetree change to match * Add initial HSIO support * Switch to IORESOURCE_REG for resource definitions Colin Foster (13): pinctrl: ocelot: allow pinctrl-ocelot to be loaded as a module pinctrl: microchip-sgpio: allow sgpio driver to be used as a module net: mdio: mscc-miim: add local dev variable to cleanup probe function net: ocelot: add interface to get regmaps when exernally controlled net: mdio: mscc-miim: add ability to be used in a non-mmio configuration pinctrl: ocelot: add ability to be used in a non-mmio configuration pinctrl: microchip-sgpio: add ability to be used in a non-mmio configuration phy: ocelot-serdes: add ability to be used in mfd configuration resource: add define macro for register address resources mfd: ocelot: add support for the vsc7512 chip via spi net: mscc: ocelot: expose ocelot wm functions net: dsa: felix: add configurable device quirks net: dsa: ocelot: add external ocelot switch control drivers/mfd/Kconfig | 24 + drivers/mfd/Makefile | 3 + drivers/mfd/ocelot-core.c | 192 +++++++ drivers/mfd/ocelot-spi.c | 313 ++++++++++++ drivers/mfd/ocelot.h | 42 ++ drivers/net/dsa/ocelot/Kconfig | 14 + drivers/net/dsa/ocelot/Makefile | 5 + drivers/net/dsa/ocelot/felix.c | 7 +- drivers/net/dsa/ocelot/felix.h | 1 + drivers/net/dsa/ocelot/felix_vsc9959.c | 1 + drivers/net/dsa/ocelot/ocelot_ext.c | 567 +++++++++++++++++++++ drivers/net/dsa/ocelot/seville_vsc9953.c | 1 + drivers/net/ethernet/mscc/ocelot_devlink.c | 31 ++ drivers/net/ethernet/mscc/ocelot_vsc7514.c | 28 - drivers/net/mdio/mdio-mscc-miim.c | 49 +- drivers/phy/mscc/phy-ocelot-serdes.c | 11 + drivers/pinctrl/Kconfig | 4 +- drivers/pinctrl/pinctrl-microchip-sgpio.c | 26 +- drivers/pinctrl/pinctrl-ocelot.c | 35 +- include/linux/ioport.h | 5 + include/soc/mscc/ocelot.h | 19 + 21 files changed, 1318 insertions(+), 60 deletions(-) create mode 100644 drivers/mfd/ocelot-core.c create mode 100644 drivers/mfd/ocelot-spi.c create mode 100644 drivers/mfd/ocelot.h create mode 100644 drivers/net/dsa/ocelot/ocelot_ext.c