diff mbox series

drm/mgag200: Fix PLL setup for g200wb and g200ew

Message ID 20220308171111.220557-1-jfalempe@redhat.com (mailing list archive)
State New, archived
Headers show
Series drm/mgag200: Fix PLL setup for g200wb and g200ew | expand

Commit Message

Jocelyn Falempe March 8, 2022, 5:11 p.m. UTC
commit f86c3ed55920ca1d874758cc290890902a6cffc4 ("drm/mgag200: Split PLL
setup into compute and update functions") introduced a regression for
g200wb and g200ew.
The PLLs are not set up properly, and VGA screen stays
black, or displays "out of range" message.

MGA1064_WB_PIX_PLLC_N/M/P was mistakenly replaced with
MGA1064_PIX_PLLC_N/M/P which have different addresses.

Patch tested on a Dell T310 with g200wb

Fixes: f86c3ed55920ca1d874758cc290890902a6cffc4
Cc: stable@vger.kernel.org
Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
---
 drivers/gpu/drm/mgag200/mgag200_pll.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

Comments

Greg KH March 8, 2022, 5:31 p.m. UTC | #1
On Tue, Mar 08, 2022 at 06:11:11PM +0100, Jocelyn Falempe wrote:
> commit f86c3ed55920ca1d874758cc290890902a6cffc4 ("drm/mgag200: Split PLL
> setup into compute and update functions") introduced a regression for
> g200wb and g200ew.

No need for all those digits in the sha1, see below:

> The PLLs are not set up properly, and VGA screen stays
> black, or displays "out of range" message.
> 
> MGA1064_WB_PIX_PLLC_N/M/P was mistakenly replaced with
> MGA1064_PIX_PLLC_N/M/P which have different addresses.
> 
> Patch tested on a Dell T310 with g200wb
> 
> Fixes: f86c3ed55920ca1d874758cc290890902a6cffc4

As per the documentation that line should read:

Fixes: f86c3ed55920 ("drm/mgag200: Split PLL setup into compute and update functions")

thanks,

greg k-h
Jocelyn Falempe March 8, 2022, 5:36 p.m. UTC | #2
On 08/03/2022 18:31, Greg KH wrote:
> On Tue, Mar 08, 2022 at 06:11:11PM +0100, Jocelyn Falempe wrote:
>> commit f86c3ed55920ca1d874758cc290890902a6cffc4 ("drm/mgag200: Split PLL
>> setup into compute and update functions") introduced a regression for
>> g200wb and g200ew.
> 
> No need for all those digits in the sha1, see below:
> 
>> The PLLs are not set up properly, and VGA screen stays
>> black, or displays "out of range" message.
>>
>> MGA1064_WB_PIX_PLLC_N/M/P was mistakenly replaced with
>> MGA1064_PIX_PLLC_N/M/P which have different addresses.
>>
>> Patch tested on a Dell T310 with g200wb
>>
>> Fixes: f86c3ed55920ca1d874758cc290890902a6cffc4
> 
> As per the documentation that line should read:
> 
> Fixes: f86c3ed55920 ("drm/mgag200: Split PLL setup into compute and update functions")

Sorry, I will send a v2 shortly.
> 
> thanks,
> 
> greg k-h
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/mgag200/mgag200_pll.c b/drivers/gpu/drm/mgag200/mgag200_pll.c
index e9ae22b4f813..52be08b744ad 100644
--- a/drivers/gpu/drm/mgag200/mgag200_pll.c
+++ b/drivers/gpu/drm/mgag200/mgag200_pll.c
@@ -404,9 +404,9 @@  mgag200_pixpll_update_g200wb(struct mgag200_pll *pixpll, const struct mgag200_pl
 		udelay(50);
 
 		/* program pixel pll register */
-		WREG_DAC(MGA1064_PIX_PLLC_N, xpixpllcn);
-		WREG_DAC(MGA1064_PIX_PLLC_M, xpixpllcm);
-		WREG_DAC(MGA1064_PIX_PLLC_P, xpixpllcp);
+		WREG_DAC(MGA1064_WB_PIX_PLLC_N, xpixpllcn);
+		WREG_DAC(MGA1064_WB_PIX_PLLC_M, xpixpllcm);
+		WREG_DAC(MGA1064_WB_PIX_PLLC_P, xpixpllcp);
 
 		udelay(50);