| Message ID | 5797913.TNu9mpgMAd@phil (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [GIT,PULL] Rockchip clock changes for 5.18 | expand |
Quoting Heiko Stuebner (2022-02-24 14:40:21) > Hi Mike, Stephen, > > please find below some Rockchip clock changes for 5.18 > > Please pull, thanks > Heiko > > The following changes since commit e783362eb54cd99b2cac8b3a9aeac942e6f6ac07: > > Linux 5.17-rc1 (2022-01-23 10:12:53 +0200) > > are available in the Git repository at: > > git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git tags/v5.18-rockchip-clk1 > > for you to fetch changes up to 10b74af310735860510a533433b1d3ab2e05a138: > > clk: rockchip: re-add rational best approximation algorithm to the fractional divider (2022-02-24 00:07:16 +0100) > > ---------------------------------------------------------------- Thanks. Pulled into clk-next
Hi Mike, Stephen, please find below some Rockchip clock changes for 5.18 Please pull, thanks Heiko The following changes since commit e783362eb54cd99b2cac8b3a9aeac942e6f6ac07: Linux 5.17-rc1 (2022-01-23 10:12:53 +0200) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git tags/v5.18-rockchip-clk1 for you to fetch changes up to 10b74af310735860510a533433b1d3ab2e05a138: clk: rockchip: re-add rational best approximation algorithm to the fractional divider (2022-02-24 00:07:16 +0100) ---------------------------------------------------------------- Improve the clocks for the rk3568 display outputs (parenting, pll-rates), use of_device_get_match_data() instead of open-coding on rk3568 and reintroduce the expected fractional-divider behaviour that disappeared with the addition of CLK_FRAC_DIVIDER_POWER_OF_TWO_PS. ---------------------------------------------------------------- Minghao Chi (CGEL ZTE) (1): clk/rockchip: Use of_device_get_match_data() Quentin Schulz (1): clk: rockchip: re-add rational best approximation algorithm to the fractional divider Sascha Hauer (3): clk: rockchip: Add more PLL rates for rk3568 clk: rockchip: drop CLK_SET_RATE_PARENT from dclk_vop* on rk3568 clk: rockchip: Add CLK_SET_RATE_PARENT to the HDMI reference clock on rk3568 drivers/clk/rockchip/clk-rk3568.c | 20 ++++++++++++-------- drivers/clk/rockchip/clk.c | 3 +++ 2 files changed, 15 insertions(+), 8 deletions(-)