@@ -1057,21 +1057,62 @@ static int df_indirect_read_broadcast(u16 node, u8 func, u16 reg, u32 *lo)
return __df_indirect_read(node, func, reg, DF_BROADCAST, lo);
}
+/* Use "reg_" prefix for raw register values. */
struct addr_ctx {
u64 ret_addr;
u32 tmp;
+ u32 reg_dram_offset;
u16 nid;
u8 inst_id;
+ u8 map_num;
};
struct data_fabric_ops {
+ u64 (*get_hi_addr_offset)(struct addr_ctx *ctx);
};
+static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx)
+{
+ return (ctx->reg_dram_offset & GENMASK_ULL(31, 20)) << 8;
+}
+
struct data_fabric_ops df2_ops = {
+ .get_hi_addr_offset = get_hi_addr_offset_df2,
};
struct data_fabric_ops *df_ops;
+static int get_dram_offset_reg(struct addr_ctx *ctx)
+{
+ /* Read D18F0x1B4 (DramOffset) */
+ if (df_indirect_read_instance(ctx->nid, 0, 0x1B4, ctx->inst_id, &ctx->reg_dram_offset))
+ return -EINVAL;
+
+ return 0;
+}
+
+static int remove_dram_offset(struct addr_ctx *ctx)
+{
+ if (get_dram_offset_reg(ctx)) {
+ pr_debug("Failed to get DRAM Offset register");
+ return -EINVAL;
+ }
+
+ ctx->map_num = 0;
+
+ /* Remove HiAddrOffset from normalized address, if enabled: */
+ if (ctx->reg_dram_offset & BIT(0)) {
+ u64 hi_addr_offset = df_ops->get_hi_addr_offset(ctx);
+
+ if (ctx->ret_addr >= hi_addr_offset) {
+ ctx->ret_addr -= hi_addr_offset;
+ ctx->map_num = 1;
+ }
+ }
+
+ return 0;
+}
+
static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
{
u64 dram_base_addr, dram_limit_addr, dram_hole_base;
@@ -1080,7 +1121,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets;
u8 intlv_addr_sel, intlv_addr_bit;
u8 num_intlv_bits, hashed_bit;
- u8 lgcy_mmio_hole_en, base = 0;
+ u8 lgcy_mmio_hole_en;
u8 cs_mask, cs_id = 0;
bool hash_enabled = false;
@@ -1099,22 +1140,13 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
ctx.nid = nid;
ctx.inst_id = umc;
- /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */
- if (df_indirect_read_instance(nid, 0, 0x1B4, umc, &ctx.tmp))
+ if (remove_dram_offset(&ctx)) {
+ pr_debug("Failed to remove DRAM offset");
goto out_err;
-
- /* Remove HiAddrOffset from normalized address, if enabled: */
- if (ctx.tmp & BIT(0)) {
- u64 hi_addr_offset = (ctx.tmp & GENMASK_ULL(31, 20)) << 8;
-
- if (norm_addr >= hi_addr_offset) {
- ctx.ret_addr -= hi_addr_offset;
- base = 1;
- }
}
/* Read D18F0x110 (DramBaseAddress). */
- if (df_indirect_read_instance(nid, 0, 0x110 + (8 * base), umc, &ctx.tmp))
+ if (df_indirect_read_instance(nid, 0, 0x110 + (8 * ctx.map_num), umc, &ctx.tmp))
goto out_err;
/* Check if address range is valid. */
@@ -1137,7 +1169,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
}
/* Read D18F0x114 (DramLimitAddress). */
- if (df_indirect_read_instance(nid, 0, 0x114 + (8 * base), umc, &ctx.tmp))
+ if (df_indirect_read_instance(nid, 0, 0x114 + (8 * ctx.map_num), umc, &ctx.tmp))
goto out_err;
intlv_num_sockets = (ctx.tmp >> 8) & 0x1;
Add helper functions to read the DramOffset register and to remove the offset from the calculated address. The helper functions will be expanded in future DF versions. Rename the "base" variable to "map_num" to indicate that this is the address map number. An address map is defined with a base and limit value. The map_num variable is used to select the proper base and limit registers to use for the address translation. Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> --- Link: https://lore.kernel.org/r/20211028175728.121452-7-yazen.ghannam@amd.com v3->v4: * Include pr_debug() on failure. * Remove leading whitespace in function pointer. v2->v3: * Was patch 7 in v2. * Dropped "df_regs" use. v1->v2: * Moved from arch/x86 to EDAC. * Add function to data_fabric_ops. drivers/edac/amd64_edac.c | 60 ++++++++++++++++++++++++++++++--------- 1 file changed, 46 insertions(+), 14 deletions(-)