| Message ID | 20220312013812.169671-1-marex@denx.de |
|---|---|
| State | Superseded |
| Headers | show |
| Series | phy: freescale: imx8m-pcie: Handle IMX8_PCIE_REFCLK_PAD_UNUSED | expand |
> -----Original Message----- > From: Marek Vasut <marex@denx.de> > Sent: 2022年3月12日 9:38 > To: linux-phy@lists.infradead.org > Cc: Marek Vasut <marex@denx.de>; Fabio Estevam <festevam@denx.de>; > Kishon Vijay Abraham I <kishon@ti.com>; Marcel Ziswiler > <marcel.ziswiler@toradex.com>; dl-linux-imx <linux-imx@nxp.com>; Peng Fan > <peng.fan@nxp.com>; Hongxing Zhu <hongxing.zhu@nxp.com>; Shawn Guo > <shawnguo@kernel.org>; Vinod Koul <vkoul@kernel.org>; > linux-arm-kernel@lists.infradead.org > Subject: [PATCH] phy: freescale: imx8m-pcie: Handle > IMX8_PCIE_REFCLK_PAD_UNUSED > > The 'fsl,refclk-pad-mode' DT property used to select clock source for PCIe PHY > can have either of three values, IMX8_PCIE_REFCLK_PAD_INPUT, > IMX8_PCIE_REFCLK_PAD_OUTPUT, IMX8_PCIE_REFCLK_PAD_UNUSED. The first > two options are handled correctly by the driver, the last one is not, this patch > implements support for the last option. > > The IMX8_PCIE_REFCLK_PAD_INPUT means PCIE_RESREF is PHY clock input, > the IMX8_PCIE_REFCLK_PAD_OUTPUT means PHY clock are sourced from SoC > internal PLL and output to PCIE_RESREF external IO pin. The last > IMX8_PCIE_REFCLK_PAD_UNUSED is a combination of previous two, PHY clock > are sourced from SoC internal PLL and not output anywhere. > > Signed-off-by: Marek Vasut <marex@denx.de> Hi Marek: Thanks for your patch. I assume that you had tested this IMX8_PCIE_REFCLK_PAD_UNUSED option. The CLK_N/P pads are not connected on the tested board, right? BTW, it's better to add the Fixes tag into the commit log. Best Regards Richard Zhu > Cc: Fabio Estevam <festevam@denx.de> > Cc: Kishon Vijay Abraham I <kishon@ti.com> > Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> > Cc: NXP Linux Team <linux-imx@nxp.com> > Cc: Peng Fan <peng.fan@nxp.com> > Cc: Richard Zhu <hongxing.zhu@nxp.com> > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: Vinod Koul <vkoul@kernel.org> > Cc: linux-arm-kernel@lists.infradead.org > To: linux-phy@lists.infradead.org > --- > drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c > b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c > index e56954063108c..7d8e6991279f4 100644 > --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c > +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c > @@ -156,15 +156,21 @@ static int imx8_pcie_phy_init(struct phy *phy) > break; > } > > - if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT) { > + if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT || > + pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) { > /* Configure the pad as input */ > val = readl(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061); > writel(val & ~ANA_PLL_CLK_OUT_TO_EXT_IO_EN, > imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061); > - } else if (pad_mode == IMX8_PCIE_REFCLK_PAD_OUTPUT) { > + } else { > /* Configure the PHY to output the refclock via pad */ > writel(ANA_PLL_CLK_OUT_TO_EXT_IO_EN, > imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061); > + } > + > + if (pad_mode == IMX8_PCIE_REFCLK_PAD_OUTPUT || > + pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) { > + /* Source clock from SoC internal PLL */ > writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL, > imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG062); > writel(AUX_PLL_REFCLK_SEL_SYS_PLL, > -- > 2.34.1
On 3/14/22 02:51, Hongxing Zhu wrote: >> -----Original Message----- >> From: Marek Vasut <marex@denx.de> >> Sent: 2022年3月12日 9:38 >> To: linux-phy@lists.infradead.org >> Cc: Marek Vasut <marex@denx.de>; Fabio Estevam <festevam@denx.de>; >> Kishon Vijay Abraham I <kishon@ti.com>; Marcel Ziswiler >> <marcel.ziswiler@toradex.com>; dl-linux-imx <linux-imx@nxp.com>; Peng Fan >> <peng.fan@nxp.com>; Hongxing Zhu <hongxing.zhu@nxp.com>; Shawn Guo >> <shawnguo@kernel.org>; Vinod Koul <vkoul@kernel.org>; >> linux-arm-kernel@lists.infradead.org >> Subject: [PATCH] phy: freescale: imx8m-pcie: Handle >> IMX8_PCIE_REFCLK_PAD_UNUSED >> >> The 'fsl,refclk-pad-mode' DT property used to select clock source for PCIe PHY >> can have either of three values, IMX8_PCIE_REFCLK_PAD_INPUT, >> IMX8_PCIE_REFCLK_PAD_OUTPUT, IMX8_PCIE_REFCLK_PAD_UNUSED. The first >> two options are handled correctly by the driver, the last one is not, this patch >> implements support for the last option. >> >> The IMX8_PCIE_REFCLK_PAD_INPUT means PCIE_RESREF is PHY clock input, >> the IMX8_PCIE_REFCLK_PAD_OUTPUT means PHY clock are sourced from SoC >> internal PLL and output to PCIE_RESREF external IO pin. The last >> IMX8_PCIE_REFCLK_PAD_UNUSED is a combination of previous two, PHY clock >> are sourced from SoC internal PLL and not output anywhere. >> >> Signed-off-by: Marek Vasut <marex@denx.de> > Hi Marek: > Thanks for your patch. > I assume that you had tested this IMX8_PCIE_REFCLK_PAD_UNUSED option. Yes > The CLK_N/P pads are not connected on the tested board, right? They are connected from MX8MP SoC to MiniPCIe slot. There is no external clock source like on the EVK, the MX8MP internal PLL is the clock source. > BTW, it's better to add the Fixes tag into the commit log. Do you think this should be considered a bugfix ?
> -----Original Message----- > From: Marek Vasut <marex@denx.de> > Sent: 2022年3月14日 10:51 > To: Hongxing Zhu <hongxing.zhu@nxp.com>; linux-phy@lists.infradead.org > Cc: Fabio Estevam <festevam@denx.de>; Kishon Vijay Abraham I > <kishon@ti.com>; Marcel Ziswiler <marcel.ziswiler@toradex.com>; > dl-linux-imx <linux-imx@nxp.com>; Peng Fan <peng.fan@nxp.com>; Shawn > Guo <shawnguo@kernel.org>; Vinod Koul <vkoul@kernel.org>; > linux-arm-kernel@lists.infradead.org > Subject: Re: [PATCH] phy: freescale: imx8m-pcie: Handle > IMX8_PCIE_REFCLK_PAD_UNUSED > > On 3/14/22 02:51, Hongxing Zhu wrote: > >> -----Original Message----- > >> From: Marek Vasut <marex@denx.de> > >> Sent: 2022年3月12日 9:38 > >> To: linux-phy@lists.infradead.org > >> Cc: Marek Vasut <marex@denx.de>; Fabio Estevam <festevam@denx.de>; > >> Kishon Vijay Abraham I <kishon@ti.com>; Marcel Ziswiler > >> <marcel.ziswiler@toradex.com>; dl-linux-imx <linux-imx@nxp.com>; Peng > >> Fan <peng.fan@nxp.com>; Hongxing Zhu <hongxing.zhu@nxp.com>; Shawn > >> Guo <shawnguo@kernel.org>; Vinod Koul <vkoul@kernel.org>; > >> linux-arm-kernel@lists.infradead.org > >> Subject: [PATCH] phy: freescale: imx8m-pcie: Handle > >> IMX8_PCIE_REFCLK_PAD_UNUSED > >> > >> The 'fsl,refclk-pad-mode' DT property used to select clock source for > >> PCIe PHY can have either of three values, IMX8_PCIE_REFCLK_PAD_INPUT, > >> IMX8_PCIE_REFCLK_PAD_OUTPUT, IMX8_PCIE_REFCLK_PAD_UNUSED. The > first > >> two options are handled correctly by the driver, the last one is not, > >> this patch implements support for the last option. > >> > >> The IMX8_PCIE_REFCLK_PAD_INPUT means PCIE_RESREF is PHY clock input, > >> the IMX8_PCIE_REFCLK_PAD_OUTPUT means PHY clock are sourced from > SoC > >> internal PLL and output to PCIE_RESREF external IO pin. The last > >> IMX8_PCIE_REFCLK_PAD_UNUSED is a combination of previous two, PHY > >> clock are sourced from SoC internal PLL and not output anywhere. > >> > >> Signed-off-by: Marek Vasut <marex@denx.de> > > Hi Marek: > > Thanks for your patch. > > I assume that you had tested this IMX8_PCIE_REFCLK_PAD_UNUSED option. > > Yes > > > The CLK_N/P pads are not connected on the tested board, right? > > They are connected from MX8MP SoC to MiniPCIe slot. > There is no external clock source like on the EVK, the MX8MP internal PLL is > the clock source. > Got that, thanks. > > BTW, it's better to add the Fixes tag into the commit log. > > Do you think this should be considered a bugfix ? Emm... It's reasonable to consider it as new added. Okay, I'm fine with it. Thanks again for your patch. Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com> Best Regards Richard Zhu
On 3/14/22 04:29, Hongxing Zhu wrote: [...] >>>> Signed-off-by: Marek Vasut <marex@denx.de> >>> Hi Marek: >>> Thanks for your patch. >>> I assume that you had tested this IMX8_PCIE_REFCLK_PAD_UNUSED option. >> >> Yes >> >>> The CLK_N/P pads are not connected on the tested board, right? >> >> They are connected from MX8MP SoC to MiniPCIe slot. >> There is no external clock source like on the EVK, the MX8MP internal PLL is >> the clock source. >> > Got that, thanks. btw. if you plan to resend the MX8MP PCIe patches (assuming they didn't get applied yet), CC me, I can provide a Tested-by . >>> BTW, it's better to add the Fixes tag into the commit log. >> >> Do you think this should be considered a bugfix ? > Emm... > It's reasonable to consider it as new added. > Okay, I'm fine with it. Thanks again for your patch. > > Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com> Let's wait for others' opinion, I'm really unsure whether this is a Fixes: or not.
> -----Original Message----- > From: Marek Vasut <marex@denx.de> > Sent: 2022年3月14日 18:53 > To: Hongxing Zhu <hongxing.zhu@nxp.com>; linux-phy@lists.infradead.org > Cc: Fabio Estevam <festevam@denx.de>; Kishon Vijay Abraham I > <kishon@ti.com>; Marcel Ziswiler <marcel.ziswiler@toradex.com>; > dl-linux-imx <linux-imx@nxp.com>; Peng Fan <peng.fan@nxp.com>; Shawn > Guo <shawnguo@kernel.org>; Vinod Koul <vkoul@kernel.org>; > linux-arm-kernel@lists.infradead.org > Subject: Re: [PATCH] phy: freescale: imx8m-pcie: Handle > IMX8_PCIE_REFCLK_PAD_UNUSED > > On 3/14/22 04:29, Hongxing Zhu wrote: > > [...] > > >>>> Signed-off-by: Marek Vasut <marex@denx.de> > >>> Hi Marek: > >>> Thanks for your patch. > >>> I assume that you had tested this IMX8_PCIE_REFCLK_PAD_UNUSED > option. > >> > >> Yes > >> > >>> The CLK_N/P pads are not connected on the tested board, right? > >> > >> They are connected from MX8MP SoC to MiniPCIe slot. > >> There is no external clock source like on the EVK, the MX8MP internal > >> PLL is the clock source. > >> > > Got that, thanks. > > btw. if you plan to resend the MX8MP PCIe patches (assuming they didn't get > applied yet), CC me, I can provide a Tested-by . Sure, I would CC you from next review cycle. It's great that you can help. Thanks. > > >>> BTW, it's better to add the Fixes tag into the commit log. > >> > >> Do you think this should be considered a bugfix ? > > Emm... > > It's reasonable to consider it as new added. > > Okay, I'm fine with it. Thanks again for your patch. > > > > Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com> > > Let's wait for others' opinion, I'm really unsure whether this is a > Fixes: or not. Okay. Best Regards Richard Zhu
On 12-03-22, 02:38, Marek Vasut wrote: > The 'fsl,refclk-pad-mode' DT property used to select clock source for > PCIe PHY can have either of three values, IMX8_PCIE_REFCLK_PAD_INPUT, > IMX8_PCIE_REFCLK_PAD_OUTPUT, IMX8_PCIE_REFCLK_PAD_UNUSED. The first > two options are handled correctly by the driver, the last one is not, > this patch implements support for the last option. > > The IMX8_PCIE_REFCLK_PAD_INPUT means PCIE_RESREF is PHY clock input, > the IMX8_PCIE_REFCLK_PAD_OUTPUT means PHY clock are sourced from SoC > internal PLL and output to PCIE_RESREF external IO pin. The last > IMX8_PCIE_REFCLK_PAD_UNUSED is a combination of previous two, PHY > clock are sourced from SoC internal PLL and not output anywhere. This does not apply on phy-next, please rebase
On 4/13/22 11:36, Vinod Koul wrote: > On 12-03-22, 02:38, Marek Vasut wrote: >> The 'fsl,refclk-pad-mode' DT property used to select clock source for >> PCIe PHY can have either of three values, IMX8_PCIE_REFCLK_PAD_INPUT, >> IMX8_PCIE_REFCLK_PAD_OUTPUT, IMX8_PCIE_REFCLK_PAD_UNUSED. The first >> two options are handled correctly by the driver, the last one is not, >> this patch implements support for the last option. >> >> The IMX8_PCIE_REFCLK_PAD_INPUT means PCIE_RESREF is PHY clock input, >> the IMX8_PCIE_REFCLK_PAD_OUTPUT means PHY clock are sourced from SoC >> internal PLL and output to PCIE_RESREF external IO pin. The last >> IMX8_PCIE_REFCLK_PAD_UNUSED is a combination of previous two, PHY >> clock are sourced from SoC internal PLL and not output anywhere. > > This does not apply on phy-next, please rebase Done, V2 is out
diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c index e56954063108c..7d8e6991279f4 100644 --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c @@ -156,15 +156,21 @@ static int imx8_pcie_phy_init(struct phy *phy) break; } - if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT) { + if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT || + pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) { /* Configure the pad as input */ val = readl(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061); writel(val & ~ANA_PLL_CLK_OUT_TO_EXT_IO_EN, imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061); - } else if (pad_mode == IMX8_PCIE_REFCLK_PAD_OUTPUT) { + } else { /* Configure the PHY to output the refclock via pad */ writel(ANA_PLL_CLK_OUT_TO_EXT_IO_EN, imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061); + } + + if (pad_mode == IMX8_PCIE_REFCLK_PAD_OUTPUT || + pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) { + /* Source clock from SoC internal PLL */ writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL, imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG062); writel(AUX_PLL_REFCLK_SEL_SYS_PLL,
The 'fsl,refclk-pad-mode' DT property used to select clock source for PCIe PHY can have either of three values, IMX8_PCIE_REFCLK_PAD_INPUT, IMX8_PCIE_REFCLK_PAD_OUTPUT, IMX8_PCIE_REFCLK_PAD_UNUSED. The first two options are handled correctly by the driver, the last one is not, this patch implements support for the last option. The IMX8_PCIE_REFCLK_PAD_INPUT means PCIE_RESREF is PHY clock input, the IMX8_PCIE_REFCLK_PAD_OUTPUT means PHY clock are sourced from SoC internal PLL and output to PCIE_RESREF external IO pin. The last IMX8_PCIE_REFCLK_PAD_UNUSED is a combination of previous two, PHY clock are sourced from SoC internal PLL and not output anywhere. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Vinod Koul <vkoul@kernel.org> Cc: linux-arm-kernel@lists.infradead.org To: linux-phy@lists.infradead.org --- drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)