| Message ID | 20220321075131.17811-3-sherry.sun@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | add ddr controller node to support EDAC on imx8mp | expand |
On 21/03/2022 08:51, Sherry Sun wrote: > i.MX8MP use synopsys V3.70a ddr controller IP, so add edac support > for i.MX8MP based on "snps,ddrc-3.80a" synopsys edac driver. > > Signed-off-by: Sherry Sun <sherry.sun@nxp.com> > --- > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > index 3f8703f3ba5b..f39da2b12ddc 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > @@ -902,6 +902,12 @@ > interrupt-parent = <&gic>; > }; > Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Best regards, Krzysztof
On Mon, Mar 21, 2022 at 03:51:31PM +0800, Sherry Sun wrote: > i.MX8MP use synopsys V3.70a ddr controller IP, so add edac support > for i.MX8MP based on "snps,ddrc-3.80a" synopsys edac driver. > > Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Applied, thanks!
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 3f8703f3ba5b..f39da2b12ddc 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -902,6 +902,12 @@ interrupt-parent = <&gic>; }; + edacmc: memory-controller@3d400000 { + compatible = "snps,ddrc-3.80a"; + reg = <0x3d400000 0x400000>; + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + }; + ddr-pmu@3d800000 { compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu"; reg = <0x3d800000 0x400000>;
i.MX8MP use synopsys V3.70a ddr controller IP, so add edac support for i.MX8MP based on "snps,ddrc-3.80a" synopsys edac driver. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 ++++++ 1 file changed, 6 insertions(+)