| Message ID | 20220318144534.17996-21-allen-kh.cheng@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add driver nodes for MT8192 SoC | expand |
Il 18/03/22 15:45, Allen-KH Cheng ha scritto: > Add dsi ndoe for mt8192 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) >
On Fri, Mar 18, 2022 at 10:45:32PM +0800, Allen-KH Cheng wrote: > Add dsi ndoe for mt8192 SoC. Minor typo: ndoe -> node. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index 59183fb6c80b..08e0dd2483d1 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -13,6 +13,7 @@ > #include <dt-bindings/pinctrl/mt8192-pinfunc.h> > #include <dt-bindings/phy/phy.h> > #include <dt-bindings/power/mt8192-power.h> > +#include <dt-bindings/reset/mt8192-resets.h> > #include <dt-bindings/reset/ti-syscon.h> > > / { > @@ -1203,6 +1204,7 @@ > compatible = "mediatek,mt8192-mmsys", "syscon"; > reg = <0 0x14000000 0 0x1000>; > #clock-cells = <1>; > + #reset-cells = <1>; > }; > > mutex: mutex@14001000 { > @@ -1327,6 +1329,20 @@ > clocks = <&mmsys CLK_MM_DISP_DITHER0>; > }; > > + dsi0: dsi@14010000 { > + compatible = "mediatek,mt8183-dsi"; > + reg = <0 0x14010000 0 0x1000>; > + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&mmsys CLK_MM_DSI0>, > + <&mmsys CLK_MM_DSI_DSI0>, > + <&mipi_tx0>; > + clock-names = "engine", "digital", "hs"; > + resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>; > + phys = <&mipi_tx0>; > + phy-names = "dphy"; > + status = "disabled"; > + }; > + > ovl_2l2: ovl@14014000 { > compatible = "mediatek,mt8192-disp-ovl-2l"; > reg = <0 0x14014000 0 0x1000>; > -- > 2.18.0 > >
On 18/03/2022 15:45, Allen-KH Cheng wrote: > Add dsi ndoe for mt8192 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index 59183fb6c80b..08e0dd2483d1 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -13,6 +13,7 @@ > #include <dt-bindings/pinctrl/mt8192-pinfunc.h> > #include <dt-bindings/phy/phy.h> > #include <dt-bindings/power/mt8192-power.h> > +#include <dt-bindings/reset/mt8192-resets.h> > #include <dt-bindings/reset/ti-syscon.h> > > / { > @@ -1203,6 +1204,7 @@ > compatible = "mediatek,mt8192-mmsys", "syscon"; > reg = <0 0x14000000 0 0x1000>; > #clock-cells = <1>; > + #reset-cells = <1>; > }; > > mutex: mutex@14001000 { > @@ -1327,6 +1329,20 @@ > clocks = <&mmsys CLK_MM_DISP_DITHER0>; > }; > > + dsi0: dsi@14010000 { > + compatible = "mediatek,mt8183-dsi"; > + reg = <0 0x14010000 0 0x1000>; > + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&mmsys CLK_MM_DSI0>, > + <&mmsys CLK_MM_DSI_DSI0>, > + <&mipi_tx0>; > + clock-names = "engine", "digital", "hs"; > + resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>; > + phys = <&mipi_tx0>; > + phy-names = "dphy"; > + status = "disabled"; We are missing the output port node. Regards, Matthias > + }; > + > ovl_2l2: ovl@14014000 { > compatible = "mediatek,mt8192-disp-ovl-2l"; > reg = <0 0x14014000 0 0x1000>;
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 59183fb6c80b..08e0dd2483d1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -13,6 +13,7 @@ #include <dt-bindings/pinctrl/mt8192-pinfunc.h> #include <dt-bindings/phy/phy.h> #include <dt-bindings/power/mt8192-power.h> +#include <dt-bindings/reset/mt8192-resets.h> #include <dt-bindings/reset/ti-syscon.h> / { @@ -1203,6 +1204,7 @@ compatible = "mediatek,mt8192-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; mutex: mutex@14001000 { @@ -1327,6 +1329,20 @@ clocks = <&mmsys CLK_MM_DISP_DITHER0>; }; + dsi0: dsi@14010000 { + compatible = "mediatek,mt8183-dsi"; + reg = <0 0x14010000 0 0x1000>; + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&mmsys CLK_MM_DSI0>, + <&mmsys CLK_MM_DSI_DSI0>, + <&mipi_tx0>; + clock-names = "engine", "digital", "hs"; + resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>; + phys = <&mipi_tx0>; + phy-names = "dphy"; + status = "disabled"; + }; + ovl_2l2: ovl@14014000 { compatible = "mediatek,mt8192-disp-ovl-2l"; reg = <0 0x14014000 0 0x1000>;
Add dsi ndoe for mt8192 SoC. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)