| Message ID | 20220318142009.2796-10-nancy.lin@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add MediaTek SoC DRM (vdosys1) support for mt8195 | expand |
Hi, Nancy: On Fri, 2022-03-18 at 22:19 +0800, Nancy.Lin wrote: > Add mtk-mutex support for mt8195 vdosys1. > The vdosys1 path component contains ovl_adaptor, merge5, > and dp_intf1. Ovl_adaptor is composed of several sub-elements. > > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com> > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > --- > drivers/soc/mediatek/mtk-mutex.c | 54 > ++++++++++++++++++++++++++++++++ > 1 file changed, 54 insertions(+) > > diff --git a/drivers/soc/mediatek/mtk-mutex.c > b/drivers/soc/mediatek/mtk-mutex.c > index cb791671d751..70e6043e99df 100644 > --- a/drivers/soc/mediatek/mtk-mutex.c > +++ b/drivers/soc/mediatek/mtk-mutex.c > @@ -129,6 +129,35 @@ > #define MT8195_MUTEX_MOD_DISP_PWM0 BIT(27) > #define MT8195_MUTEX_MOD_DISP_PWM1 BIT(28) > > +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 BIT(0) > +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 BIT(1) > +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 BIT(2) > +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 BIT(3) > +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 BIT(4) > +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 BIT(5) > +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 BIT(6) > +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 BIT(7) > +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 BIT(8) > +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 BIT(9) > +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 BIT(10) > +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 BIT(11) > +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 BIT(12) > +#define MT8195_MUTEX_MOD_DISP1_VPP2_DL_RELAY BIT(13) > +#define MT8195_MUTEX_MOD_DISP1_VPP3_DL_RELAY BIT(14) > +#define MT8195_MUTEX_MOD_DISP1_VDO0_DSC_DL_ASYNC BIT(15) > +#define MT8195_MUTEX_MOD_DISP1_VDO0_MERGE_DL_ASYNC BIT(16) > +#define MT8195_MUTEX_MOD_DISP1_VDO1_OUT_DL_RELAY BIT(17) > +#define MT8195_MUTEX_MOD_DISP1_DISP_MIXER BIT(18) > +#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 BIT(19) > +#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 BIT(20) > +#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 BIT(21) > +#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 BIT(22) > +#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 BIT(23) > +#define MT8195_MUTEX_MOD_DISP1_HDR_MLOAD BIT(24) > +#define MT8195_MUTEX_MOD_DISP1_DPI0 BIT(25) > +#define MT8195_MUTEX_MOD_DISP1_DPI1 BIT(26) > +#define MT8195_MUTEX_MOD_DISP1_DP_INTF0 BIT(27) > + > #define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10) > #define MT2712_MUTEX_MOD_DISP_OVL0 BIT(11) > #define MT2712_MUTEX_MOD_DISP_OVL1 BIT(12) > @@ -332,6 +361,27 @@ static const u64 > mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { > [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0, > [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0, > [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0, > + [DDP_COMPONENT_OVL_ADAPTOR] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 > | I would like to expose each mod instead of ovl adaptor. ovl adaptor is an application that combine these mod to achieve ovl function, maybe another application would combine part of these mod to achieve another function. Let application to decide the combination. Regards, CK > + MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 > | > + MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 > | > + MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 > | > + MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 > | > + MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 > | > + MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 > | > + MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 > | > + MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 > | > + MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 > | > + MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 > | > + MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 > | > + MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE > 0 | > + MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE > 1 | > + MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE > 0 | > + MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE > 1 | > + MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE > 0 | > + MT8195_MUTEX_MOD_DISP1_HDR_MLOAD > | > + MT8195_MUTEX_MOD_DISP1_DISP_MIXER > , > + [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4, > + [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0, > }; > > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = { > @@ -517,6 +567,9 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex, > case DDP_COMPONENT_DP_INTF0: > sof_id = MUTEX_SOF_DP_INTF0; > break; > + case DDP_COMPONENT_DP_INTF1: > + sof_id = MUTEX_SOF_DP_INTF1; > + break; > default: > if (mtx->data->mutex_mod[id] <= BIT(31)) { > offset = DISP_REG_MUTEX_MOD(mtx->data- > >mutex_mod_reg, > @@ -557,6 +610,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex > *mutex, > case DDP_COMPONENT_DPI0: > case DDP_COMPONENT_DPI1: > case DDP_COMPONENT_DP_INTF0: > + case DDP_COMPONENT_DP_INTF1: > writel_relaxed(MUTEX_SOF_SINGLE_MODE, > mtx->regs + > DISP_REG_MUTEX_SOF(mtx->data- > >mutex_sof_reg,
Hi CK, Thanks for the review. On Tue, 2022-03-22 at 10:27 +0800, CK Hu wrote: > Hi, Nancy: > > On Fri, 2022-03-18 at 22:19 +0800, Nancy.Lin wrote: > > Add mtk-mutex support for mt8195 vdosys1. > > The vdosys1 path component contains ovl_adaptor, merge5, > > and dp_intf1. Ovl_adaptor is composed of several sub-elements. > > > > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com> > > Reviewed-by: AngeloGioacchino Del Regno < > > angelogioacchino.delregno@collabora.com> > > --- > > drivers/soc/mediatek/mtk-mutex.c | 54 > > ++++++++++++++++++++++++++++++++ > > 1 file changed, 54 insertions(+) > > > > diff --git a/drivers/soc/mediatek/mtk-mutex.c > > b/drivers/soc/mediatek/mtk-mutex.c > > index cb791671d751..70e6043e99df 100644 > > --- a/drivers/soc/mediatek/mtk-mutex.c > > +++ b/drivers/soc/mediatek/mtk-mutex.c > > @@ -129,6 +129,35 @@ > > #define MT8195_MUTEX_MOD_DISP_PWM0 BIT(27) > > #define MT8195_MUTEX_MOD_DISP_PWM1 BIT(28) > > > > +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 BIT(0) > > +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 BIT(1) > > +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 BIT(2) > > +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 BIT(3) > > +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 BIT(4) > > +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 BIT(5) > > +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 BIT(6) > > +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 BIT(7) > > +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 BIT(8) > > +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 BIT(9) > > +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 BIT(10) > > +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 BIT(11) > > +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 BIT(12) > > +#define MT8195_MUTEX_MOD_DISP1_VPP2_DL_RELAY BIT(13) > > +#define MT8195_MUTEX_MOD_DISP1_VPP3_DL_RELAY BIT(14) > > +#define MT8195_MUTEX_MOD_DISP1_VDO0_DSC_DL_ASYNC BIT(15) > > +#define MT8195_MUTEX_MOD_DISP1_VDO0_MERGE_DL_ASYNC BIT(16) > > +#define MT8195_MUTEX_MOD_DISP1_VDO1_OUT_DL_RELAY BIT(17) > > +#define MT8195_MUTEX_MOD_DISP1_DISP_MIXER BIT(18) > > +#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 BIT(19) > > +#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 BIT(20) > > +#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 BIT(21) > > +#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 BIT(22) > > +#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 BIT(23) > > +#define MT8195_MUTEX_MOD_DISP1_HDR_MLOAD BIT(24) > > +#define MT8195_MUTEX_MOD_DISP1_DPI0 BIT(25) > > +#define MT8195_MUTEX_MOD_DISP1_DPI1 BIT(26) > > +#define MT8195_MUTEX_MOD_DISP1_DP_INTF0 BIT(27) > > + > > #define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10) > > #define MT2712_MUTEX_MOD_DISP_OVL0 BIT(11) > > #define MT2712_MUTEX_MOD_DISP_OVL1 BIT(12) > > @@ -332,6 +361,27 @@ static const u64 > > mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0, > > [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0, > > [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0, > > + [DDP_COMPONENT_OVL_ADAPTOR] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 > > > > > I would like to expose each mod instead of ovl adaptor. ovl adaptor > is > an application that combine these mod to achieve ovl function, maybe > another application would combine part of these mod to achieve > another > function. Let application to decide the combination. > > Regards, > CK > OK, I will separate ovl_adaptor component in next revision. Regards, Nancy > > + MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 > > > > > > > + MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 > > > > > > > + MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 > > > > > > > + MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 > > > > > > > + MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 > > > > > > > + MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 > > > > > > > + MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 > > > > > > > + MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 > > > > > > > + MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 > > > > > > > + MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 > > > > > > > + MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 > > > > > > > + MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE > > 0 | > > + MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE > > 1 | > > + MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE > > 0 | > > + MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE > > 1 | > > + MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE > > 0 | > > + MT8195_MUTEX_MOD_DISP1_HDR_MLOAD > > > > > > > + MT8195_MUTEX_MOD_DISP1_DISP_MIXER > > , > > + [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4, > > + [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0, > > }; > > > > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = { > > @@ -517,6 +567,9 @@ void mtk_mutex_add_comp(struct mtk_mutex > > *mutex, > > case DDP_COMPONENT_DP_INTF0: > > sof_id = MUTEX_SOF_DP_INTF0; > > break; > > + case DDP_COMPONENT_DP_INTF1: > > + sof_id = MUTEX_SOF_DP_INTF1; > > + break; > > default: > > if (mtx->data->mutex_mod[id] <= BIT(31)) { > > offset = DISP_REG_MUTEX_MOD(mtx->data- > > > mutex_mod_reg, > > > > @@ -557,6 +610,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex > > *mutex, > > case DDP_COMPONENT_DPI0: > > case DDP_COMPONENT_DPI1: > > case DDP_COMPONENT_DP_INTF0: > > + case DDP_COMPONENT_DP_INTF1: > > writel_relaxed(MUTEX_SOF_SINGLE_MODE, > > mtx->regs + > > DISP_REG_MUTEX_SOF(mtx->data- > > > mutex_sof_reg, > >
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index cb791671d751..70e6043e99df 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -129,6 +129,35 @@ #define MT8195_MUTEX_MOD_DISP_PWM0 BIT(27) #define MT8195_MUTEX_MOD_DISP_PWM1 BIT(28) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 BIT(0) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 BIT(1) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 BIT(2) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 BIT(3) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 BIT(4) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 BIT(5) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 BIT(6) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 BIT(7) +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 BIT(8) +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 BIT(9) +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 BIT(10) +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 BIT(11) +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 BIT(12) +#define MT8195_MUTEX_MOD_DISP1_VPP2_DL_RELAY BIT(13) +#define MT8195_MUTEX_MOD_DISP1_VPP3_DL_RELAY BIT(14) +#define MT8195_MUTEX_MOD_DISP1_VDO0_DSC_DL_ASYNC BIT(15) +#define MT8195_MUTEX_MOD_DISP1_VDO0_MERGE_DL_ASYNC BIT(16) +#define MT8195_MUTEX_MOD_DISP1_VDO1_OUT_DL_RELAY BIT(17) +#define MT8195_MUTEX_MOD_DISP1_DISP_MIXER BIT(18) +#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 BIT(19) +#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 BIT(20) +#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 BIT(21) +#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 BIT(22) +#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 BIT(23) +#define MT8195_MUTEX_MOD_DISP1_HDR_MLOAD BIT(24) +#define MT8195_MUTEX_MOD_DISP1_DPI0 BIT(25) +#define MT8195_MUTEX_MOD_DISP1_DPI1 BIT(26) +#define MT8195_MUTEX_MOD_DISP1_DP_INTF0 BIT(27) + #define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10) #define MT2712_MUTEX_MOD_DISP_OVL0 BIT(11) #define MT2712_MUTEX_MOD_DISP_OVL1 BIT(12) @@ -332,6 +361,27 @@ static const u64 mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0, [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0, [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0, + [DDP_COMPONENT_OVL_ADAPTOR] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 | + MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 | + MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 | + MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 | + MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 | + MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 | + MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 | + MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 | + MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 | + MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 | + MT8195_MUTEX_MOD_DISP1_HDR_MLOAD | + MT8195_MUTEX_MOD_DISP1_DISP_MIXER, + [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4, + [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0, }; static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = { @@ -517,6 +567,9 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex, case DDP_COMPONENT_DP_INTF0: sof_id = MUTEX_SOF_DP_INTF0; break; + case DDP_COMPONENT_DP_INTF1: + sof_id = MUTEX_SOF_DP_INTF1; + break; default: if (mtx->data->mutex_mod[id] <= BIT(31)) { offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, @@ -557,6 +610,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex, case DDP_COMPONENT_DPI0: case DDP_COMPONENT_DPI1: case DDP_COMPONENT_DP_INTF0: + case DDP_COMPONENT_DP_INTF1: writel_relaxed(MUTEX_SOF_SINGLE_MODE, mtx->regs + DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,