Message ID | 20220318144534.17996-5-allen-kh.cheng@mediatek.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Add driver nodes for MT8192 SoC | expand |
Il 18/03/22 15:45, Allen-KH Cheng ha scritto: > Add SCP node for mt8192 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++ > 1 file changed, 12 insertions(+) >
On Fri, Mar 18, 2022 at 10:45:16PM +0800, Allen-KH Cheng wrote: > Add SCP node for mt8192 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: NĂcolas F. R. A. Prado <nfraprado@collabora.com> > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index 9e1b563bebab..195d50894df4 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -706,6 +706,18 @@ > status = "disabled"; > }; > > + scp: scp@10500000 { > + compatible = "mediatek,mt8192-scp"; > + reg = <0 0x10500000 0 0x100000>, > + <0 0x10700000 0 0x8000>, > + <0 0x10720000 0 0xe0000>; > + reg-names = "sram", "l1tcm", "cfg"; > + interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&infracfg CLK_INFRA_SCPSYS>; > + clock-names = "main"; > + status = "disabled"; > + }; > + > nor_flash: spi@11234000 { > compatible = "mediatek,mt8192-nor"; > reg = <0 0x11234000 0 0xe0>; > -- > 2.18.0 > >
On 18/03/2022 15:45, Allen-KH Cheng wrote: > Add SCP node for mt8192 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Applied, thanks > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index 9e1b563bebab..195d50894df4 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -706,6 +706,18 @@ > status = "disabled"; > }; > > + scp: scp@10500000 { > + compatible = "mediatek,mt8192-scp"; > + reg = <0 0x10500000 0 0x100000>, > + <0 0x10700000 0 0x8000>, > + <0 0x10720000 0 0xe0000>; > + reg-names = "sram", "l1tcm", "cfg"; > + interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&infracfg CLK_INFRA_SCPSYS>; > + clock-names = "main"; > + status = "disabled"; > + }; > + > nor_flash: spi@11234000 { > compatible = "mediatek,mt8192-nor"; > reg = <0 0x11234000 0 0xe0>;
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 9e1b563bebab..195d50894df4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -706,6 +706,18 @@ status = "disabled"; }; + scp: scp@10500000 { + compatible = "mediatek,mt8192-scp"; + reg = <0 0x10500000 0 0x100000>, + <0 0x10700000 0 0x8000>, + <0 0x10720000 0 0xe0000>; + reg-names = "sram", "l1tcm", "cfg"; + interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&infracfg CLK_INFRA_SCPSYS>; + clock-names = "main"; + status = "disabled"; + }; + nor_flash: spi@11234000 { compatible = "mediatek,mt8192-nor"; reg = <0 0x11234000 0 0xe0>;
Add SCP node for mt8192 SoC. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)