| Message ID | 20220318144534.17996-18-allen-kh.cheng@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add driver nodes for MT8192 SoC | expand |
Il 18/03/22 15:45, Allen-KH Cheng ha scritto: > Add dpi node for mt8192 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++ > 1 file changed, 11 insertions(+) >
On 18/03/2022 15:45, Allen-KH Cheng wrote: > Add dpi node for mt8192 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index 71ad3adeed51..a77d405dd508 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -1236,6 +1236,17 @@ > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > }; > > + dpi0: dpi@14016000 { > + compatible = "mediatek,mt8192-dpi"; > + reg = <0 0x14016000 0 0x1000>; > + interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&mmsys CLK_MM_DPI_DPI0>, > + <&mmsys CLK_MM_DISP_DPI0>, > + <&apmixedsys CLK_APMIXED_TVDPLL>; > + clock-names = "pixel", "engine", "pll"; > + status = "disabled"; We are missing the output port node here. Regards, Matthias > + }; > + > iommu0: m4u@1401d000 { > compatible = "mediatek,mt8192-m4u"; > reg = <0 0x1401d000 0 0x1000>;
Hi Matthias, On Fri, 2022-03-25 at 16:24 +0100, Matthias Brugger wrote: > > On 18/03/2022 15:45, Allen-KH Cheng wrote: > > Add dpi node for mt8192 SoC. > > > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > > --- > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++ > > 1 file changed, 11 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > index 71ad3adeed51..a77d405dd508 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > @@ -1236,6 +1236,17 @@ > > power-domains = <&spm > > MT8192_POWER_DOMAIN_DISP>; > > }; > > > > + dpi0: dpi@14016000 { > > + compatible = "mediatek,mt8192-dpi"; > > + reg = <0 0x14016000 0 0x1000>; > > + interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH > > 0>; > > + clocks = <&mmsys CLK_MM_DPI_DPI0>, > > + <&mmsys CLK_MM_DISP_DPI0>, > > + <&apmixedsys CLK_APMIXED_TVDPLL>; > > + clock-names = "pixel", "engine", "pll"; > > + status = "disabled"; > > We are missing the output port node here. > > Regards, > Matthias > We will add output port in mt8192-asurada.dtsi (inlude mt8192.dtsi) for board level. Do we need to add any futher information in binding? Thanks, Allen > > + }; > > + > > iommu0: m4u@1401d000 { > > compatible = "mediatek,mt8192-m4u"; > > reg = <0 0x1401d000 0 0x1000>;
On 29/03/2022 09:45, allen-kh.cheng wrote: > Hi Matthias, > > On Fri, 2022-03-25 at 16:24 +0100, Matthias Brugger wrote: >> >> On 18/03/2022 15:45, Allen-KH Cheng wrote: >>> Add dpi node for mt8192 SoC. >>> >>> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> >>> --- >>> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++ >>> 1 file changed, 11 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi >>> b/arch/arm64/boot/dts/mediatek/mt8192.dtsi >>> index 71ad3adeed51..a77d405dd508 100644 >>> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi >>> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi >>> @@ -1236,6 +1236,17 @@ >>> power-domains = <&spm >>> MT8192_POWER_DOMAIN_DISP>; >>> }; >>> >>> + dpi0: dpi@14016000 { >>> + compatible = "mediatek,mt8192-dpi"; >>> + reg = <0 0x14016000 0 0x1000>; >>> + interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH >>> 0>; >>> + clocks = <&mmsys CLK_MM_DPI_DPI0>, >>> + <&mmsys CLK_MM_DISP_DPI0>, >>> + <&apmixedsys CLK_APMIXED_TVDPLL>; >>> + clock-names = "pixel", "engine", "pll"; >>> + status = "disabled"; >> >> We are missing the output port node here. >> >> Regards, >> Matthias >> > > We will add output port in mt8192-asurada.dtsi (inlude mt8192.dtsi) for > board level. > Got it, patch now applied. > Do we need to add any futher information in binding? > Hm, probably we should mark the output port as optional? Can you check how other bindings manage that? Thanks, Matthias > Thanks, > Allen > >>> + }; >>> + >>> iommu0: m4u@1401d000 { >>> compatible = "mediatek,mt8192-m4u"; >>> reg = <0 0x1401d000 0 0x1000>; >
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 71ad3adeed51..a77d405dd508 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1236,6 +1236,17 @@ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; }; + dpi0: dpi@14016000 { + compatible = "mediatek,mt8192-dpi"; + reg = <0 0x14016000 0 0x1000>; + interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&mmsys CLK_MM_DPI_DPI0>, + <&mmsys CLK_MM_DISP_DPI0>, + <&apmixedsys CLK_APMIXED_TVDPLL>; + clock-names = "pixel", "engine", "pll"; + status = "disabled"; + }; + iommu0: m4u@1401d000 { compatible = "mediatek,mt8192-m4u"; reg = <0 0x1401d000 0 0x1000>;
Add dpi node for mt8192 SoC. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+)