diff mbox series

[1/2] target/riscv: optimize condition assign for scale < 0

Message ID 20220325085902.29500-1-liweiwei@iscas.ac.cn (mailing list archive)
State New, archived
Headers show
Series [1/2] target/riscv: optimize condition assign for scale < 0 | expand

Commit Message

Weiwei Li March 25, 2022, 8:59 a.m. UTC 
for some cases, scale is always equal or less than 0, since lmul is not larger than 3

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

Comments

Frank Chang March 25, 2022, 9:26 a.m. UTC | #1 
Reviewed-by: Frank Chang <frank.chang@sifive.com>

On Fri, Mar 25, 2022 at 5:00 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:

> for some cases, scale is always equal or less than 0, since lmul is not
> larger than 3
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 8 +++-----
>  1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 4ea7e41e1a..2878ca3132 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -1198,7 +1198,7 @@ GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true)
>  static inline uint32_t MAXSZ(DisasContext *s)
>  {
>      int scale = s->lmul - 3;
> -    return scale < 0 ? s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen <<
> scale;
> +    return s->cfg_ptr->vlen >> -scale;
>  }
>
>  static bool opivv_check(DisasContext *s, arg_rmrr *a)
> @@ -3597,8 +3597,7 @@ static bool trans_vrgather_vx(DisasContext *s,
> arg_rmrr *a)
>
>      if (a->vm && s->vl_eq_vlmax) {
>          int scale = s->lmul - (s->sew + 3);
> -        int vlmax = scale < 0 ?
> -                       s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen <<
> scale;
> +        int vlmax = s->cfg_ptr->vlen >> -scale;
>          TCGv_i64 dest = tcg_temp_new_i64();
>
>          if (a->rs1 == 0) {
> @@ -3630,8 +3629,7 @@ static bool trans_vrgather_vi(DisasContext *s,
> arg_rmrr *a)
>
>      if (a->vm && s->vl_eq_vlmax) {
>          int scale = s->lmul - (s->sew + 3);
> -        int vlmax = scale < 0 ?
> -                       s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen <<
> scale;
> +        int vlmax = s->cfg_ptr->vlen >> -scale;
>          if (a->rs1 >= vlmax) {
>              tcg_gen_gvec_dup_imm(MO_64, vreg_ofs(s, a->rd),
>                                   MAXSZ(s), MAXSZ(s), 0);
> --
> 2.17.1
>
>
>
Alistair Francis March 28, 2022, 1:11 a.m. UTC | #2 
On Fri, Mar 25, 2022 at 7:03 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> for some cases, scale is always equal or less than 0, since lmul is not larger than 3
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 8 +++-----
>  1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 4ea7e41e1a..2878ca3132 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -1198,7 +1198,7 @@ GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true)
>  static inline uint32_t MAXSZ(DisasContext *s)
>  {
>      int scale = s->lmul - 3;
> -    return scale < 0 ? s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
> +    return s->cfg_ptr->vlen >> -scale;
>  }
>
>  static bool opivv_check(DisasContext *s, arg_rmrr *a)
> @@ -3597,8 +3597,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
>
>      if (a->vm && s->vl_eq_vlmax) {
>          int scale = s->lmul - (s->sew + 3);
> -        int vlmax = scale < 0 ?
> -                       s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
> +        int vlmax = s->cfg_ptr->vlen >> -scale;
>          TCGv_i64 dest = tcg_temp_new_i64();
>
>          if (a->rs1 == 0) {
> @@ -3630,8 +3629,7 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
>
>      if (a->vm && s->vl_eq_vlmax) {
>          int scale = s->lmul - (s->sew + 3);
> -        int vlmax = scale < 0 ?
> -                       s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
> +        int vlmax = s->cfg_ptr->vlen >> -scale;
>          if (a->rs1 >= vlmax) {
>              tcg_gen_gvec_dup_imm(MO_64, vreg_ofs(s, a->rd),
>                                   MAXSZ(s), MAXSZ(s), 0);
> --
> 2.17.1
>
>
Alistair Francis March 28, 2022, 4:01 a.m. UTC | #3 
On Fri, Mar 25, 2022 at 7:03 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> for some cases, scale is always equal or less than 0, since lmul is not larger than 3
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 8 +++-----
>  1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 4ea7e41e1a..2878ca3132 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -1198,7 +1198,7 @@ GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true)
>  static inline uint32_t MAXSZ(DisasContext *s)
>  {
>      int scale = s->lmul - 3;
> -    return scale < 0 ? s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
> +    return s->cfg_ptr->vlen >> -scale;
>  }
>
>  static bool opivv_check(DisasContext *s, arg_rmrr *a)
> @@ -3597,8 +3597,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
>
>      if (a->vm && s->vl_eq_vlmax) {
>          int scale = s->lmul - (s->sew + 3);
> -        int vlmax = scale < 0 ?
> -                       s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
> +        int vlmax = s->cfg_ptr->vlen >> -scale;
>          TCGv_i64 dest = tcg_temp_new_i64();
>
>          if (a->rs1 == 0) {
> @@ -3630,8 +3629,7 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
>
>      if (a->vm && s->vl_eq_vlmax) {
>          int scale = s->lmul - (s->sew + 3);
> -        int vlmax = scale < 0 ?
> -                       s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
> +        int vlmax = s->cfg_ptr->vlen >> -scale;
>          if (a->rs1 >= vlmax) {
>              tcg_gen_gvec_dup_imm(MO_64, vreg_ofs(s, a->rd),
>                                   MAXSZ(s), MAXSZ(s), 0);
> --
> 2.17.1
>
>
diff mbox series

Patch

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 4ea7e41e1a..2878ca3132 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1198,7 +1198,7 @@  GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true)
 static inline uint32_t MAXSZ(DisasContext *s)
 {
     int scale = s->lmul - 3;
-    return scale < 0 ? s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
+    return s->cfg_ptr->vlen >> -scale;
 }
 
 static bool opivv_check(DisasContext *s, arg_rmrr *a)
@@ -3597,8 +3597,7 @@  static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
 
     if (a->vm && s->vl_eq_vlmax) {
         int scale = s->lmul - (s->sew + 3);
-        int vlmax = scale < 0 ?
-                       s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
+        int vlmax = s->cfg_ptr->vlen >> -scale;
         TCGv_i64 dest = tcg_temp_new_i64();
 
         if (a->rs1 == 0) {
@@ -3630,8 +3629,7 @@  static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
 
     if (a->vm && s->vl_eq_vlmax) {
         int scale = s->lmul - (s->sew + 3);
-        int vlmax = scale < 0 ?
-                       s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
+        int vlmax = s->cfg_ptr->vlen >> -scale;
         if (a->rs1 >= vlmax) {
             tcg_gen_gvec_dup_imm(MO_64, vreg_ofs(s, a->rd),
                                  MAXSZ(s), MAXSZ(s), 0);