| Message ID | 20220318144534.17996-22-allen-kh.cheng@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add driver nodes for MT8192 SoC | expand |
On Fri, Mar 18, 2022 at 10:45:33PM +0800, Allen-KH Cheng wrote: > Add gce info for display nodes > - It's required to get drivers' CMDQ support It's better to use complete sentences instead of bullet points like this. Also you could be more descriptive in the commit message. Suggestion: Add GCE (Global Command Engine) properties to the display nodes in order to enable the usage of the CMDQ (Command Queue), which is required for operating the display. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index 08e0dd2483d1..f0f0f067c023 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -1203,6 +1203,9 @@ > mmsys: syscon@14000000 { > compatible = "mediatek,mt8192-mmsys", "syscon"; > reg = <0 0x14000000 0 0x1000>; > + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>, > + <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; > #clock-cells = <1>; > #reset-cells = <1>; > }; > @@ -1212,6 +1215,8 @@ > reg = <0 0x14001000 0 0x1000>; > interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>; > clocks = <&mmsys CLK_MM_DISP_MUTEX0>; > + mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, > + <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; > }; > > smi_common: smi@14002000 { > @@ -1253,6 +1258,7 @@ > iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, > <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; > }; > > ovl_2l0: ovl@14006000 { > @@ -1263,6 +1269,7 @@ > clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; > iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, > <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; > }; > > rdma0: rdma@14007000 { > @@ -1274,6 +1281,7 @@ > mediatek,larb = <&larb0>; > mediatek,rdma-fifo-size = <5120>; > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; > }; > > color0: color@14009000 { > @@ -1283,6 +1291,7 @@ > interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>; > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > clocks = <&mmsys CLK_MM_DISP_COLOR0>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; > }; > > ccorr0: ccorr@1400a000 { > @@ -1291,6 +1300,7 @@ > interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > clocks = <&mmsys CLK_MM_DISP_CCORR0>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; > }; > > aal0: aal@1400b000 { > @@ -1300,6 +1310,7 @@ > interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>; > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > clocks = <&mmsys CLK_MM_DISP_AAL0>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; > }; > > gamma0: gamma@1400c000 { > @@ -1309,6 +1320,7 @@ > interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>; > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > clocks = <&mmsys CLK_MM_DISP_GAMMA0>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; > }; > > postmask0: postmask@1400d000 { > @@ -1318,6 +1330,7 @@ > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; > iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; > }; > > dither0: dither@1400e000 { > @@ -1327,6 +1340,7 @@ > interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>; > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > clocks = <&mmsys CLK_MM_DISP_DITHER0>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; > }; > > dsi0: dsi@14010000 { > @@ -1351,6 +1365,7 @@ > clocks = <&mmsys CLK_MM_DISP_OVL2_2L>; > iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, > <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; > }; > > rdma4: rdma@14015000 { > @@ -1361,6 +1376,7 @@ > clocks = <&mmsys CLK_MM_DISP_RDMA4>; > iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>; > mediatek,rdma-fifo-size = <2048>; > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; > }; > > dpi0: dpi@14016000 { > -- > 2.18.0 > >
Il 18/03/22 15:45, Allen-KH Cheng ha scritto: > Add gce info for display nodes > - It's required to get drivers' CMDQ support > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
On 18/03/2022 15:45, Allen-KH Cheng wrote: > Add gce info for display nodes > - It's required to get drivers' CMDQ support > What keeps us from adding that in the display nodes in patch 18/22 of this series? When doing so, please mention in the commit message that we then need to add the GCE to the mmsys node. Regards, Matthias > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index 08e0dd2483d1..f0f0f067c023 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -1203,6 +1203,9 @@ > mmsys: syscon@14000000 { > compatible = "mediatek,mt8192-mmsys", "syscon"; > reg = <0 0x14000000 0 0x1000>; > + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>, > + <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; > #clock-cells = <1>; > #reset-cells = <1>; > }; > @@ -1212,6 +1215,8 @@ > reg = <0 0x14001000 0 0x1000>; > interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>; > clocks = <&mmsys CLK_MM_DISP_MUTEX0>; > + mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, > + <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; > }; > > smi_common: smi@14002000 { > @@ -1253,6 +1258,7 @@ > iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, > <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; > }; > > ovl_2l0: ovl@14006000 { > @@ -1263,6 +1269,7 @@ > clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; > iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, > <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; > }; > > rdma0: rdma@14007000 { > @@ -1274,6 +1281,7 @@ > mediatek,larb = <&larb0>; > mediatek,rdma-fifo-size = <5120>; > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; > }; > > color0: color@14009000 { > @@ -1283,6 +1291,7 @@ > interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>; > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > clocks = <&mmsys CLK_MM_DISP_COLOR0>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; > }; > > ccorr0: ccorr@1400a000 { > @@ -1291,6 +1300,7 @@ > interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > clocks = <&mmsys CLK_MM_DISP_CCORR0>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; > }; > > aal0: aal@1400b000 { > @@ -1300,6 +1310,7 @@ > interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>; > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > clocks = <&mmsys CLK_MM_DISP_AAL0>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; > }; > > gamma0: gamma@1400c000 { > @@ -1309,6 +1320,7 @@ > interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>; > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > clocks = <&mmsys CLK_MM_DISP_GAMMA0>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; > }; > > postmask0: postmask@1400d000 { > @@ -1318,6 +1330,7 @@ > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; > iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; > }; > > dither0: dither@1400e000 { > @@ -1327,6 +1340,7 @@ > interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>; > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > clocks = <&mmsys CLK_MM_DISP_DITHER0>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; > }; > > dsi0: dsi@14010000 { > @@ -1351,6 +1365,7 @@ > clocks = <&mmsys CLK_MM_DISP_OVL2_2L>; > iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, > <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; > }; > > rdma4: rdma@14015000 { > @@ -1361,6 +1376,7 @@ > clocks = <&mmsys CLK_MM_DISP_RDMA4>; > iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>; > mediatek,rdma-fifo-size = <2048>; > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; > }; > > dpi0: dpi@14016000 {
Hi On Mon, 2022-03-28 at 13:06 +0200, Matthias Brugger wrote: > > On 18/03/2022 15:45, Allen-KH Cheng wrote: > > Add gce info for display nodes > > - It's required to get drivers' CMDQ support > > > > What keeps us from adding that in the display nodes in patch 18/22 of > this > series? When doing so, please mention in the commit message that we > then need to > add the GCE to the mmsys node. > > Regards, > Matthias > There is no particular reason for this patch. I will squash this patch into 18/22([PATCH v4 18/22] arm64: dts: mt8192: Add display nodes) Thanks, Allen > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > > --- > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++ > > 1 file changed, 16 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > index 08e0dd2483d1..f0f0f067c023 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > @@ -1203,6 +1203,9 @@ > > mmsys: syscon@14000000 { > > compatible = "mediatek,mt8192-mmsys", "syscon"; > > reg = <0 0x14000000 0 0x1000>; > > + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>, > > + <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>; > > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX > > 0 0x1000>; > > #clock-cells = <1>; > > #reset-cells = <1>; > > }; > > @@ -1212,6 +1215,8 @@ > > reg = <0 0x14001000 0 0x1000>; > > interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH > > 0>; > > clocks = <&mmsys CLK_MM_DISP_MUTEX0>; > > + mediatek,gce-events = > > <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, > > + <CMDQ_EVENT_DISP_STREAM_D > > ONE_ENG_EVENT_1>; > > }; > > > > smi_common: smi@14002000 { > > @@ -1253,6 +1258,7 @@ > > iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, > > <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; > > power-domains = <&spm > > MT8192_POWER_DOMAIN_DISP>; > > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX > > 0x5000 0x1000>; > > }; > > > > ovl_2l0: ovl@14006000 { > > @@ -1263,6 +1269,7 @@ > > clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; > > iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, > > <&iommu0 > > M4U_PORT_L1_OVL_2L_RDMA0_HDR>; > > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX > > 0x6000 0x1000>; > > }; > > > > rdma0: rdma@14007000 { > > @@ -1274,6 +1281,7 @@ > > mediatek,larb = <&larb0>; > > mediatek,rdma-fifo-size = <5120>; > > power-domains = <&spm > > MT8192_POWER_DOMAIN_DISP>; > > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX > > 0x7000 0x1000>; > > }; > > > > color0: color@14009000 { > > @@ -1283,6 +1291,7 @@ > > interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH > > 0>; > > power-domains = <&spm > > MT8192_POWER_DOMAIN_DISP>; > > clocks = <&mmsys CLK_MM_DISP_COLOR0>; > > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX > > 0x9000 0x1000>; > > }; > > > > ccorr0: ccorr@1400a000 { > > @@ -1291,6 +1300,7 @@ > > interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH > > 0>; > > power-domains = <&spm > > MT8192_POWER_DOMAIN_DISP>; > > clocks = <&mmsys CLK_MM_DISP_CCORR0>; > > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX > > 0xa000 0x1000>; > > }; > > > > aal0: aal@1400b000 { > > @@ -1300,6 +1310,7 @@ > > interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH > > 0>; > > power-domains = <&spm > > MT8192_POWER_DOMAIN_DISP>; > > clocks = <&mmsys CLK_MM_DISP_AAL0>; > > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX > > 0xb000 0x1000>; > > }; > > > > gamma0: gamma@1400c000 { > > @@ -1309,6 +1320,7 @@ > > interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH > > 0>; > > power-domains = <&spm > > MT8192_POWER_DOMAIN_DISP>; > > clocks = <&mmsys CLK_MM_DISP_GAMMA0>; > > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX > > 0xc000 0x1000>; > > }; > > > > postmask0: postmask@1400d000 { > > @@ -1318,6 +1330,7 @@ > > power-domains = <&spm > > MT8192_POWER_DOMAIN_DISP>; > > clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; > > iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>; > > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX > > 0xd000 0x1000>; > > }; > > > > dither0: dither@1400e000 { > > @@ -1327,6 +1340,7 @@ > > interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH > > 0>; > > power-domains = <&spm > > MT8192_POWER_DOMAIN_DISP>; > > clocks = <&mmsys CLK_MM_DISP_DITHER0>; > > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX > > 0xe000 0x1000>; > > }; > > > > dsi0: dsi@14010000 { > > @@ -1351,6 +1365,7 @@ > > clocks = <&mmsys CLK_MM_DISP_OVL2_2L>; > > iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, > > <&iommu0 > > M4U_PORT_L1_OVL_2L_RDMA2_HDR>; > > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX > > 0x4000 0x1000>; > > }; > > > > rdma4: rdma@14015000 { > > @@ -1361,6 +1376,7 @@ > > clocks = <&mmsys CLK_MM_DISP_RDMA4>; > > iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>; > > mediatek,rdma-fifo-size = <2048>; > > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX > > 0x5000 0x1000>; > > }; > > > > dpi0: dpi@14016000 {
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 08e0dd2483d1..f0f0f067c023 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1203,6 +1203,9 @@ mmsys: syscon@14000000 { compatible = "mediatek,mt8192-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; @@ -1212,6 +1215,8 @@ reg = <0 0x14001000 0 0x1000>; interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&mmsys CLK_MM_DISP_MUTEX0>; + mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, + <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; }; smi_common: smi@14002000 { @@ -1253,6 +1258,7 @@ iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; }; ovl_2l0: ovl@14006000 { @@ -1263,6 +1269,7 @@ clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; }; rdma0: rdma@14007000 { @@ -1274,6 +1281,7 @@ mediatek,larb = <&larb0>; mediatek,rdma-fifo-size = <5120>; power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; }; color0: color@14009000 { @@ -1283,6 +1291,7 @@ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_COLOR0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; }; ccorr0: ccorr@1400a000 { @@ -1291,6 +1300,7 @@ interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_CCORR0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; }; aal0: aal@1400b000 { @@ -1300,6 +1310,7 @@ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_AAL0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; }; gamma0: gamma@1400c000 { @@ -1309,6 +1320,7 @@ interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_GAMMA0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; }; postmask0: postmask@1400d000 { @@ -1318,6 +1330,7 @@ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; }; dither0: dither@1400e000 { @@ -1327,6 +1340,7 @@ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_DITHER0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; }; dsi0: dsi@14010000 { @@ -1351,6 +1365,7 @@ clocks = <&mmsys CLK_MM_DISP_OVL2_2L>; iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; }; rdma4: rdma@14015000 { @@ -1361,6 +1376,7 @@ clocks = <&mmsys CLK_MM_DISP_RDMA4>; iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>; mediatek,rdma-fifo-size = <2048>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; }; dpi0: dpi@14016000 {
Add gce info for display nodes - It's required to get drivers' CMDQ support Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)