diff mbox series

[v5,1/4] arm64: dts: mt8192: Add PCIe node

Message ID 20220330133816.30806-2-allen-kh.cheng@mediatek.com (mailing list archive)
State New, archived
Headers show
Series Add driver nodes for MT8192 SoC | expand

Commit Message

Allen-KH Cheng March 30, 2022, 1:38 p.m. UTC 
Add PCIe node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 35 ++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

Comments

Matthias Brugger March 31, 2022, 11:56 a.m. UTC | #1 
On 30/03/2022 15:38, Allen-KH Cheng wrote:
> Add PCIe node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

I wonder why you left Nicolas Reviewed-by but not the one from Angelo. Anyway 
when sending a new version, be sure to drop the reviewed-by tags if there are 
substantial changes in the patch. We can argue if changing the clock names is a 
substantial change or not. Maybe that's why you left just one reviewed-by tag ;)
I'm just joking, I'll add the other tag myself.

Applied thanks.

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 35 ++++++++++++++++++++++++
>   1 file changed, 35 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 579abbf4488e..69e8d1934d53 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -716,6 +716,41 @@
>   			status = "disabled";
>   		};
>   
> +		pcie: pcie@11230000 {
> +			compatible = "mediatek,mt8192-pcie";
> +			device_type = "pci";
> +			reg = <0 0x11230000 0 0x2000>;
> +			reg-names = "pcie-mac";
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			clocks = <&infracfg CLK_INFRA_PCIE_PL_P_250M>,
> +				 <&infracfg CLK_INFRA_PCIE_TL_26M>,
> +				 <&infracfg CLK_INFRA_PCIE_TL_96M>,
> +				 <&infracfg CLK_INFRA_PCIE_TL_32K>,
> +				 <&infracfg CLK_INFRA_PCIE_PERI_26M>,
> +				 <&infracfg CLK_INFRA_PCIE_TOP_H_133M>;
> +			clock-names = "pl_250m", "tl_26m", "tl_96m",
> +				      "tl_32k", "peri_26m", "top_133m";
> +			assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
> +			interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
> +			bus-range = <0x00 0xff>;
> +			ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>,
> +				 <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>;
> +			#interrupt-cells = <1>;
> +			interrupt-map-mask = <0 0 0 7>;
> +			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
> +					<0 0 0 2 &pcie_intc0 1>,
> +					<0 0 0 3 &pcie_intc0 2>,
> +					<0 0 0 4 &pcie_intc0 3>;
> +
> +			pcie_intc0: interrupt-controller {
> +				interrupt-controller;
> +				#address-cells = <0>;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
>   		nor_flash: spi@11234000 {
>   			compatible = "mediatek,mt8192-nor";
>   			reg = <0 0x11234000 0 0xe0>;
Allen-KH Cheng March 31, 2022, 12:33 p.m. UTC | #2 
Hi Matthias,

On Thu, 2022-03-31 at 13:56 +0200, Matthias Brugger wrote:
> 
> On 30/03/2022 15:38, Allen-KH Cheng wrote:
> > Add PCIe node for mt8192 SoC.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> 
> I wonder why you left Nicolas Reviewed-by but not the one from
> Angelo. Anyway 
> when sending a new version, be sure to drop the reviewed-by tags if
> there are 
> substantial changes in the patch. We can argue if changing the clock
> names is a 
> substantial change or not. Maybe that's why you left just one
> reviewed-by tag ;)
> I'm just joking, I'll add the other tag myself.
> 
> Applied thanks.
> 

This is my carelessness.

I don't notice Angelo's reply.

I'll pay more attention to that next time.

Best regards,
Allen

> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 35
> > ++++++++++++++++++++++++
> >   1 file changed, 35 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 579abbf4488e..69e8d1934d53 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -716,6 +716,41 @@
> >   			status = "disabled";
> >   		};
> >   
> > +		pcie: pcie@11230000 {
> > +			compatible = "mediatek,mt8192-pcie";
> > +			device_type = "pci";
> > +			reg = <0 0x11230000 0 0x2000>;
> > +			reg-names = "pcie-mac";
> > +			#address-cells = <3>;
> > +			#size-cells = <2>;
> > +			clocks = <&infracfg CLK_INFRA_PCIE_PL_P_250M>,
> > +				 <&infracfg CLK_INFRA_PCIE_TL_26M>,
> > +				 <&infracfg CLK_INFRA_PCIE_TL_96M>,
> > +				 <&infracfg CLK_INFRA_PCIE_TL_32K>,
> > +				 <&infracfg CLK_INFRA_PCIE_PERI_26M>,
> > +				 <&infracfg CLK_INFRA_PCIE_TOP_H_133M>;
> > +			clock-names = "pl_250m", "tl_26m", "tl_96m",
> > +				      "tl_32k", "peri_26m", "top_133m";
> > +			assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
> > +			assigned-clock-parents = <&topckgen
> > CLK_TOP_MAINPLL_D6_D4>;
> > +			interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			bus-range = <0x00 0xff>;
> > +			ranges = <0x82000000 0 0x12000000 0x0
> > 0x12000000 0 0x0800000>,
> > +				 <0x81000000 0 0x12800000 0x0
> > 0x12800000 0 0x0800000>;
> > +			#interrupt-cells = <1>;
> > +			interrupt-map-mask = <0 0 0 7>;
> > +			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
> > +					<0 0 0 2 &pcie_intc0 1>,
> > +					<0 0 0 3 &pcie_intc0 2>,
> > +					<0 0 0 4 &pcie_intc0 3>;
> > +
> > +			pcie_intc0: interrupt-controller {
> > +				interrupt-controller;
> > +				#address-cells = <0>;
> > +				#interrupt-cells = <1>;
> > +			};
> > +		};
> > +
> >   		nor_flash: spi@11234000 {
> >   			compatible = "mediatek,mt8192-nor";
> >   			reg = <0 0x11234000 0 0xe0>;
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 579abbf4488e..69e8d1934d53 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -716,6 +716,41 @@ 
 			status = "disabled";
 		};
 
+		pcie: pcie@11230000 {
+			compatible = "mediatek,mt8192-pcie";
+			device_type = "pci";
+			reg = <0 0x11230000 0 0x2000>;
+			reg-names = "pcie-mac";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			clocks = <&infracfg CLK_INFRA_PCIE_PL_P_250M>,
+				 <&infracfg CLK_INFRA_PCIE_TL_26M>,
+				 <&infracfg CLK_INFRA_PCIE_TL_96M>,
+				 <&infracfg CLK_INFRA_PCIE_TL_32K>,
+				 <&infracfg CLK_INFRA_PCIE_PERI_26M>,
+				 <&infracfg CLK_INFRA_PCIE_TOP_H_133M>;
+			clock-names = "pl_250m", "tl_26m", "tl_96m",
+				      "tl_32k", "peri_26m", "top_133m";
+			assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
+			interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
+			bus-range = <0x00 0xff>;
+			ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>,
+				 <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+					<0 0 0 2 &pcie_intc0 1>,
+					<0 0 0 3 &pcie_intc0 2>,
+					<0 0 0 4 &pcie_intc0 3>;
+
+			pcie_intc0: interrupt-controller {
+				interrupt-controller;
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+			};
+		};
+
 		nor_flash: spi@11234000 {
 			compatible = "mediatek,mt8192-nor";
 			reg = <0 0x11234000 0 0xe0>;