diff mbox series

[2/4] dt-bindings: cpufreq: mediatek: add mt8186 cpufreq dt-bindings

Message ID 20220307122151.11666-3-jia-wei.chang@mediatek.com (mailing list archive)
State New, archived
Headers show
Series cpufreq: mediatek: introduce mtk cpufreq | expand

Commit Message

Jia-wei Chang (張佳偉) March 7, 2022, 12:21 p.m. UTC
1. add cci property.
2. add example of MT8186.

Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.corp-partner.google.com>
---
 .../bindings/cpufreq/cpufreq-mediatek.yaml    | 41 +++++++++++++++++++
 1 file changed, 41 insertions(+)

Comments

Krzysztof Kozlowski March 7, 2022, 6:59 p.m. UTC | #1
On 07/03/2022 13:21, Tim Chang wrote:
> 1. add cci property.
> 2. add example of MT8186.

One logical change at a time. Are these related? Why entirely new
example just for "cci" node? Maybe this should be part of existing example?

> 
> Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.corp-partner.google.com>
> ---
>  .../bindings/cpufreq/cpufreq-mediatek.yaml    | 41 +++++++++++++++++++
>  1 file changed, 41 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.yaml
> index 584946eb3790..d3ce17fd8fcf 100644
> --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.yaml
> +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.yaml
> @@ -48,6 +48,10 @@ properties:
>        When absent, the voltage scaling flow is handled by hardware, hence no
>        software "voltage tracking" is needed.
>  
> +  cci:
> +    description:
> +      Phandle of the cci to be linked with the phandle of CPU if present.

This does not look like a standard type, so you need type.



Best regards,
Krzysztof
Rob Herring (Arm) March 10, 2022, 8:44 p.m. UTC | #2
On Mon, Mar 07, 2022 at 08:21:49PM +0800, Tim Chang wrote:
> 1. add cci property.
> 2. add example of MT8186.
> 
> Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.corp-partner.google.com>
> ---
>  .../bindings/cpufreq/cpufreq-mediatek.yaml    | 41 +++++++++++++++++++
>  1 file changed, 41 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.yaml
> index 584946eb3790..d3ce17fd8fcf 100644
> --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.yaml
> +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.yaml
> @@ -48,6 +48,10 @@ properties:
>        When absent, the voltage scaling flow is handled by hardware, hence no
>        software "voltage tracking" is needed.
>  
> +  cci:
> +    description:
> +      Phandle of the cci to be linked with the phandle of CPU if present.

We already have a binding for this. See cci-control-port.

> +
>    "#cooling-cells":
>      description:
>        For details, please refer to
Jia-wei Chang (張佳偉) March 24, 2022, 9:42 a.m. UTC | #3
On Mon, 2022-03-07 at 19:59 +0100, Krzysztof Kozlowski wrote:
> On 07/03/2022 13:21, Tim Chang wrote:
> > 1. add cci property.
> > 2. add example of MT8186.
> 
> One logical change at a time. Are these related? Why entirely new
> example just for "cci" node? Maybe this should be part of existing
> example?

Yes, the cci property is required in some SoC, e.g. mt8183 and mt8186,
because cpu and cci share the same power supplies.
I will update the commit message and add an example of mt8186 to
present usage of cci.

> 
> > 
> > Signed-off-by: Jia-Wei Chang <
> > jia-wei.chang@mediatek.corp-partner.google.com>
> > ---
> >  .../bindings/cpufreq/cpufreq-mediatek.yaml    | 41
> > +++++++++++++++++++
> >  1 file changed, 41 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-
> > mediatek.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-
> > mediatek.yaml
> > index 584946eb3790..d3ce17fd8fcf 100644
> > --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-
> > mediatek.yaml
> > +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-
> > mediatek.yaml
> > @@ -48,6 +48,10 @@ properties:
> >        When absent, the voltage scaling flow is handled by
> > hardware, hence no
> >        software "voltage tracking" is needed.
> >  
> > +  cci:
> > +    description:
> > +      Phandle of the cci to be linked with the phandle of CPU if
> > present.
> 
> This does not look like a standard type, so you need type.

Sure, I will add the type for it in the next version.

> 
> 
> 
> Best regards,
> Krzysztof
Krzysztof Kozlowski March 24, 2022, 10:35 a.m. UTC | #4
On 24/03/2022 10:42, Jia-Wei Chang wrote:
> On Mon, 2022-03-07 at 19:59 +0100, Krzysztof Kozlowski wrote:
>> On 07/03/2022 13:21, Tim Chang wrote:
>>> 1. add cci property.
>>> 2. add example of MT8186.
>>
>> One logical change at a time. Are these related? Why entirely new
>> example just for "cci" node? Maybe this should be part of existing
>> example?
> 
> Yes, the cci property is required in some SoC, e.g. mt8183 and mt8186,
> because cpu and cci share the same power supplies.

I asked why this cannot be part of existing example.

> I will update the commit message and add an example of mt8186 to
> present usage of cci.

You added the example here, didn't you?

Best regards,
Krzysztof
Jia-wei Chang (張佳偉) April 1, 2022, 1:32 p.m. UTC | #5
On Thu, 2022-03-24 at 11:35 +0100, Krzysztof Kozlowski wrote:
> On 24/03/2022 10:42, Jia-Wei Chang wrote:
> > On Mon, 2022-03-07 at 19:59 +0100, Krzysztof Kozlowski wrote:
> > > On 07/03/2022 13:21, Tim Chang wrote:
> > > > 1. add cci property.
> > > > 2. add example of MT8186.
> > > 
> > > One logical change at a time. Are these related? Why entirely new
> > > example just for "cci" node? Maybe this should be part of
> > > existing
> > > example?
> > 
> > Yes, the cci property is required in some SoC, e.g. mt8183 and
> > mt8186,
> > because cpu and cci share the same power supplies.
> 
> I asked why this cannot be part of existing example.

I misunderstood that.
I will update the complete example in the next version.

> 
> > I will update the commit message and add an example of mt8186 to
> > present usage of cci.
> 
> You added the example here, didn't you?

Yes, I did add it here.

> 
> Best regards,
> Krzysztof
Jia-wei Chang (張佳偉) April 6, 2022, 12:49 p.m. UTC | #6
On Thu, 2022-03-10 at 14:44 -0600, Rob Herring wrote:
> On Mon, Mar 07, 2022 at 08:21:49PM +0800, Tim Chang wrote:
> > 1. add cci property.
> > 2. add example of MT8186.
> > 
> > Signed-off-by: Jia-Wei Chang <
> > jia-wei.chang@mediatek.corp-partner.google.com>
> > ---
> >  .../bindings/cpufreq/cpufreq-mediatek.yaml    | 41
> > +++++++++++++++++++
> >  1 file changed, 41 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-
> > mediatek.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-
> > mediatek.yaml
> > index 584946eb3790..d3ce17fd8fcf 100644
> > --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-
> > mediatek.yaml
> > +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-
> > mediatek.yaml
> > @@ -48,6 +48,10 @@ properties:
> >        When absent, the voltage scaling flow is handled by
> > hardware, hence no
> >        software "voltage tracking" is needed.
> >  
> > +  cci:
> > +    description:
> > +      Phandle of the cci to be linked with the phandle of CPU if
> > present.
> 
> We already have a binding for this. See cci-control-port.

Hi Rob,

Pardon me for my late reply.

It seems that "cci-control-port" is hardware IP from ARM.
But mediatek-cpufreq uses MTK internal CCI hardware IP.
I think I should keep this change here.

Thanks.

> 
> > +
> >    "#cooling-cells":
> >      description:
> >        For details, please refer to
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.yaml
index 584946eb3790..d3ce17fd8fcf 100644
--- a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.yaml
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.yaml
@@ -48,6 +48,10 @@  properties:
       When absent, the voltage scaling flow is handled by hardware, hence no
       software "voltage tracking" is needed.
 
+  cci:
+    description:
+      Phandle of the cci to be linked with the phandle of CPU if present.
+
   "#cooling-cells":
     description:
       For details, please refer to
@@ -129,3 +133,40 @@  examples:
       /* ... */
 
     };
+
+  - |
+    /* Example 3 (MT8186 SoC) */
+    #include <dt-bindings/clock/mt8186-clk.h>
+    cluster0_opp: opp-table-0 {
+      compatible = "operating-points-v2";
+      opp-shared;
+      opp0_00: opp-500000000 {
+        opp-hz = /bits/ 64 <500000000>;
+        opp-microvolt = <600000>;
+        opp-level = <15>;
+        required-opps = <&opp2_00>;
+      };
+
+      /* ... */
+
+    };
+
+    cpus {
+      #address-cells = <1>;
+      #size-cells = <0>;
+      cpu1: cpu@1 {
+        device_type = "cpu";
+        compatible = "arm,cortex-a55";
+        reg = <0x0100>;
+        enable-method = "psci";
+        clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, <&apmixedsys CLK_APMIXED_MAINPLL>;
+        clock-names = "cpu", "intermediate";
+        operating-points-v2 = <&cluster0_opp>;
+        proc-supply = <&mt6358_vproc12_reg>;
+        sram-supply = <&mt6358_vsram_proc12_reg>;
+        cci = <&cci>;
+      };
+
+      /* ... */
+
+    };