| Message ID | 20220407105420.10765-1-kavyasree.kotagiri@microchip.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | spi: atmel,quadspi: Define lan966x QSPI | expand |
On Thu, Apr 07, 2022 at 04:24:20PM +0530, Kavyasree Kotagiri wrote: > @@ -19,6 +19,7 @@ properties: > - microchip,sam9x60-qspi > - microchip,sama7g5-qspi > - microchip,sama7g5-ospi > + - microchip,lan966x-qspi Generally DT compatibles should be for specific SoCs rather than having wildcards in them, even if that means you have to list a lot of SoCs. Having used wildcards in the past doesn't mean it's a good idea to continue adding them!
> > @@ -19,6 +19,7 @@ properties: > > - microchip,sam9x60-qspi > > - microchip,sama7g5-qspi > > - microchip,sama7g5-ospi > > + - microchip,lan966x-qspi > > Generally DT compatibles should be for specific SoCs rather than having > wildcards in them, even if that means you have to list a lot of SoCs. > Having used wildcards in the past doesn't mean it's a good idea to > continue adding them! The subject should also be prefixed with "dt-bindings: ". Mark, I did a git log on Documentation/devicetree/bindings/spi/atmel,quadspi.yaml and all the subjects are without "dt-bindings:" although the original patch was with that prefix [1]. Is that intended? -michael [1] https://lore.kernel.org/linux-devicetree/163962128492.2075495.3678727080606971257.b4-ty@kernel.org/
On Thu, Apr 07, 2022 at 01:23:45PM +0200, Michael Walle wrote: > > > + - microchip,lan966x-qspi > > Generally DT compatibles should be for specific SoCs rather than having > > wildcards in them, even if that means you have to list a lot of SoCs. > > Having used wildcards in the past doesn't mean it's a good idea to > > continue adding them! > The subject should also be prefixed with "dt-bindings: ". I tend to complain about people doing that. > Mark, I did a git log on > Documentation/devicetree/bindings/spi/atmel,quadspi.yaml and all the > subjects are without "dt-bindings:" although the original patch was with > that prefix [1]. Is that intended? Yes.
Am 2022-04-07 13:31, schrieb Mark Brown: > On Thu, Apr 07, 2022 at 01:23:45PM +0200, Michael Walle wrote: >> The subject should also be prefixed with "dt-bindings: ". > > I tend to complain about people doing that. After all it is mentioned to use that prefix in Documentation/devicetree/bindings/submitting-patches.rst. I try to remember when submitting SPI related bindings. -michael
On 07/04/2022 13:41, Michael Walle wrote: > Am 2022-04-07 13:31, schrieb Mark Brown: >> On Thu, Apr 07, 2022 at 01:23:45PM +0200, Michael Walle wrote: >>> The subject should also be prefixed with "dt-bindings: ". >> >> I tend to complain about people doing that. > > After all it is mentioned to use that prefix in > Documentation/devicetree/bindings/submitting-patches.rst. I try to > remember when submitting SPI related bindings. From my point of view, the dt-bindings prefix is still expected, just after "spi:" (and other Marks' subsystems), because that's I am filtering the bindings. Your submissions had the prefix in wrong place, this one patch does not have it all. :( Best regards, Krzysztof
On 07/04/2022 12:54, Kavyasree Kotagiri wrote: > LAN966x SoC supports 3 QSPI controllers. Each of them support > data and clock frequency upto 100Mhz DDR and QUAD protocol. > > Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> > --- > Documentation/devicetree/bindings/spi/atmel,quadspi.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml > index 1d493add4053..100d6e7f2748 100644 > --- a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml > +++ b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml > @@ -19,6 +19,7 @@ properties: > - microchip,sam9x60-qspi > - microchip,sama7g5-qspi > - microchip,sama7g5-ospi > + - microchip,lan966x-qspi Expect the comment you got about wildcard, please also put it in alphabetical order. As you can check, the other entries are ordered. Best regards, Krzysztof
On 4/7/22 13:54, Kavyasree Kotagiri wrote: > LAN966x SoC supports 3 QSPI controllers. Each of them support > data and clock frequency upto 100Mhz DDR and QUAD protocol. How is this IP different than microchip,sama7g5-qspi? Does this speed limitation come from the IP itself or from the board that you're using? Neither of these instances support octal mode? Cheers, ta > > Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> > --- > Documentation/devicetree/bindings/spi/atmel,quadspi.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml > index 1d493add4053..100d6e7f2748 100644 > --- a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml > +++ b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml > @@ -19,6 +19,7 @@ properties: > - microchip,sam9x60-qspi > - microchip,sama7g5-qspi > - microchip,sama7g5-ospi > + - microchip,lan966x-qspi > > reg: > items:
> > LAN966x SoC supports 3 QSPI controllers. Each of them support > > data and clock frequency upto 100Mhz DDR and QUAD protocol. > > How is this IP different than microchip,sama7g5-qspi? Does this speed > limitation come from the IP itself or from the board that you're using? > > Neither of these instances support octal mode? > Thanks for your comments. All the three instances support only QUAD protocol. You are correct. There is no difference from sama7g5-qspi. Please ignore this patch. I will send next version of dt patches where I will use "microchip,sama7g5-qspi" for all my qspi nodes. > Cheers, > ta > > > > > Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> > > --- > > Documentation/devicetree/bindings/spi/atmel,quadspi.yaml | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml > b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml > > index 1d493add4053..100d6e7f2748 100644 > > --- a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml > > +++ b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml > > @@ -19,6 +19,7 @@ properties: > > - microchip,sam9x60-qspi > > - microchip,sama7g5-qspi > > - microchip,sama7g5-ospi > > + - microchip,lan966x-qspi > > > > reg: > > items:
> > > LAN966x SoC supports 3 QSPI controllers. Each of them support > > > data and clock frequency upto 100Mhz DDR and QUAD protocol. > > > > How is this IP different than microchip,sama7g5-qspi? Does this speed > > limitation come from the IP itself or from the board that you're using? > > > > Neither of these instances support octal mode? > > > Thanks for your comments. All the three instances support only QUAD > protocol. > You are correct. There is no difference from sama7g5-qspi. Please ignore > this patch. I will send next version of dt patches where I will use > "microchip,sama7g5-qspi" for all my qspi nodes. Are you sure? There is a max frequency property in Tudor's sama7g5-qspi driver (200/133MHz) which doesn't match neither the LAN9668 manual (which states 150MHz on QSPI0 and 100MHZ on QSPI1, funny enough there is no mention of QSPI2) nor does it match the max frequency set in the downstream linux driver (24 MHz). -michael
diff --git a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml index 1d493add4053..100d6e7f2748 100644 --- a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml +++ b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml @@ -19,6 +19,7 @@ properties: - microchip,sam9x60-qspi - microchip,sama7g5-qspi - microchip,sama7g5-ospi + - microchip,lan966x-qspi reg: items:
LAN966x SoC supports 3 QSPI controllers. Each of them support data and clock frequency upto 100Mhz DDR and QUAD protocol. Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> --- Documentation/devicetree/bindings/spi/atmel,quadspi.yaml | 1 + 1 file changed, 1 insertion(+)