| Message ID | 20220408013034.673418-1-nfraprado@collabora.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/bridge: anx7625: Use uint8 for lane-swing arrays | expand |
Il 08/04/22 03:30, Nícolas F. R. A. Prado ha scritto: > As defined in the anx7625 dt-binding, the analogix,lane0-swing and > analogix,lane1-swing properties are uint8 arrays. Yet, the driver was > reading the array as if it were of uint32 and masking to 8-bit before > writing to the registers. This means that a devicetree written in > accordance to the dt-binding would have its values incorrectly parsed. > > Fix the issue by reading the array as uint8 and storing them as uint8 > internally, so that we can also drop the masking when writing the > registers. > > Fixes: fd0310b6fe7d ("drm/bridge: anx7625: add MIPI DPI input feature") > Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
On Fri, 8 Apr 2022 at 10:21, AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> wrote: > > Il 08/04/22 03:30, Nícolas F. R. A. Prado ha scritto: > > As defined in the anx7625 dt-binding, the analogix,lane0-swing and > > analogix,lane1-swing properties are uint8 arrays. Yet, the driver was > > reading the array as if it were of uint32 and masking to 8-bit before > > writing to the registers. This means that a devicetree written in > > accordance to the dt-binding would have its values incorrectly parsed. > > > > Fix the issue by reading the array as uint8 and storing them as uint8 > > internally, so that we can also drop the masking when writing the > > registers. > > > > Fixes: fd0310b6fe7d ("drm/bridge: anx7625: add MIPI DPI input feature") > > Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> > > > > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Applied to drm-misc-next
diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c index 6516f9570b86..19a1a90ccff3 100644 --- a/drivers/gpu/drm/bridge/analogix/anx7625.c +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c @@ -1486,12 +1486,12 @@ static void anx7625_dp_adjust_swing(struct anx7625_data *ctx) for (i = 0; i < ctx->pdata.dp_lane0_swing_reg_cnt; i++) anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, DP_TX_LANE0_SWING_REG0 + i, - ctx->pdata.lane0_reg_data[i] & 0xFF); + ctx->pdata.lane0_reg_data[i]); for (i = 0; i < ctx->pdata.dp_lane1_swing_reg_cnt; i++) anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, DP_TX_LANE1_SWING_REG0 + i, - ctx->pdata.lane1_reg_data[i] & 0xFF); + ctx->pdata.lane1_reg_data[i]); } static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on) @@ -1598,7 +1598,7 @@ static int anx7625_get_swing_setting(struct device *dev, num_regs = DP_TX_SWING_REG_CNT; pdata->dp_lane0_swing_reg_cnt = num_regs; - of_property_read_u32_array(dev->of_node, "analogix,lane0-swing", + of_property_read_u8_array(dev->of_node, "analogix,lane0-swing", pdata->lane0_reg_data, num_regs); } @@ -1608,7 +1608,7 @@ static int anx7625_get_swing_setting(struct device *dev, num_regs = DP_TX_SWING_REG_CNT; pdata->dp_lane1_swing_reg_cnt = num_regs; - of_property_read_u32_array(dev->of_node, "analogix,lane1-swing", + of_property_read_u8_array(dev->of_node, "analogix,lane1-swing", pdata->lane1_reg_data, num_regs); } diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.h b/drivers/gpu/drm/bridge/analogix/anx7625.h index edbbfe410a56..e257a84db962 100644 --- a/drivers/gpu/drm/bridge/analogix/anx7625.h +++ b/drivers/gpu/drm/bridge/analogix/anx7625.h @@ -426,9 +426,9 @@ struct anx7625_platform_data { int mipi_lanes; int audio_en; int dp_lane0_swing_reg_cnt; - int lane0_reg_data[DP_TX_SWING_REG_CNT]; + u8 lane0_reg_data[DP_TX_SWING_REG_CNT]; int dp_lane1_swing_reg_cnt; - int lane1_reg_data[DP_TX_SWING_REG_CNT]; + u8 lane1_reg_data[DP_TX_SWING_REG_CNT]; u32 low_power_mode; struct device_node *mipi_host_node; };
As defined in the anx7625 dt-binding, the analogix,lane0-swing and analogix,lane1-swing properties are uint8 arrays. Yet, the driver was reading the array as if it were of uint32 and masking to 8-bit before writing to the registers. This means that a devicetree written in accordance to the dt-binding would have its values incorrectly parsed. Fix the issue by reading the array as uint8 and storing them as uint8 internally, so that we can also drop the masking when writing the registers. Fixes: fd0310b6fe7d ("drm/bridge: anx7625: add MIPI DPI input feature") Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> --- drivers/gpu/drm/bridge/analogix/anx7625.c | 8 ++++---- drivers/gpu/drm/bridge/analogix/anx7625.h | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-)