| Message ID | 20220408162108.184583-12-jagan@amarulasolutions.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm: bridge: Add Samsung MIPI DSIM bridge | expand |
Hi Jagan, Thank you for the patch. On Fri, Apr 08, 2022 at 09:51:08PM +0530, Jagan Teki wrote: > Samsung MIPI DSIM master can also be found in i.MX8MM SoC. > > Add compatible and associated driver_data for it. > > v1: > * none > > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> > --- > drivers/gpu/drm/bridge/samsung-dsim.c | 34 +++++++++++++++++++++++++++ > 1 file changed, 34 insertions(+) > > diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c > index 71bbaf19f530..d91510a51981 100644 > --- a/drivers/gpu/drm/bridge/samsung-dsim.c > +++ b/drivers/gpu/drm/bridge/samsung-dsim.c > @@ -360,6 +360,24 @@ static const unsigned int exynos5433_reg_values[] = { > [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c), > }; > > +static const unsigned int imx8mm_dsim_reg_values[] = { > + [RESET_TYPE] = DSIM_SWRST, > + [PLL_TIMER] = 500, > + [STOP_STATE_CNT] = 0xf, > + [PHYCTRL_ULPS_EXIT] = 0, > + [PHYCTRL_VREG_LP] = 0, > + [PHYCTRL_SLEW_UP] = 0, > + [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), > + [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), > + [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), > + [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x26), > + [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), > + [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), > + [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x08), > + [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), > + [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), > +}; Most of these values don't seem to be specific to a particular SoC integration, but should be tuned for the board and the connected DSI sink. That's out of scope for this patch of course. > + > static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = { > .reg_ofs = exynos_reg_ofs, > .plltmr_reg = 0x50, > @@ -426,6 +444,18 @@ static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = { > .platform_init = true, > }; > > +static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = { > + .reg_ofs = exynos5433_reg_ofs, > + .plltmr_reg = 0xa0, > + .has_clklane_stop = 1, > + .num_clks = 2, > + .max_freq = 2100, > + .wait_for_reset = 0, > + .num_bits_resol = 12, > + .pll_p_offset = 14, > + .reg_values = imx8mm_dsim_reg_values, > +}; I haven't verified the values, the rest looks good to me. Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > + > static const struct of_device_id samsung_dsim_of_match[] = { > { > .compatible = "samsung,exynos3250-mipi-dsi", > @@ -447,6 +477,10 @@ static const struct of_device_id samsung_dsim_of_match[] = { > .compatible = "samsung,exynos5433-mipi-dsi", > .data = &exynos5433_dsi_driver_data > }, > + { > + .compatible = "fsl,imx8mm-mipi-dsim", > + .data = &imx8mm_dsi_driver_data > + }, > { /* sentinel. */ } > }; >
diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index 71bbaf19f530..d91510a51981 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -360,6 +360,24 @@ static const unsigned int exynos5433_reg_values[] = { [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c), }; +static const unsigned int imx8mm_dsim_reg_values[] = { + [RESET_TYPE] = DSIM_SWRST, + [PLL_TIMER] = 500, + [STOP_STATE_CNT] = 0xf, + [PHYCTRL_ULPS_EXIT] = 0, + [PHYCTRL_VREG_LP] = 0, + [PHYCTRL_SLEW_UP] = 0, + [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), + [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), + [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), + [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x26), + [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), + [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), + [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x08), + [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), + [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), +}; + static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = { .reg_ofs = exynos_reg_ofs, .plltmr_reg = 0x50, @@ -426,6 +444,18 @@ static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = { .platform_init = true, }; +static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = { + .reg_ofs = exynos5433_reg_ofs, + .plltmr_reg = 0xa0, + .has_clklane_stop = 1, + .num_clks = 2, + .max_freq = 2100, + .wait_for_reset = 0, + .num_bits_resol = 12, + .pll_p_offset = 14, + .reg_values = imx8mm_dsim_reg_values, +}; + static const struct of_device_id samsung_dsim_of_match[] = { { .compatible = "samsung,exynos3250-mipi-dsi", @@ -447,6 +477,10 @@ static const struct of_device_id samsung_dsim_of_match[] = { .compatible = "samsung,exynos5433-mipi-dsi", .data = &exynos5433_dsi_driver_data }, + { + .compatible = "fsl,imx8mm-mipi-dsim", + .data = &imx8mm_dsi_driver_data + }, { /* sentinel. */ } };
Samsung MIPI DSIM master can also be found in i.MX8MM SoC. Add compatible and associated driver_data for it. v1: * none Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> --- drivers/gpu/drm/bridge/samsung-dsim.c | 34 +++++++++++++++++++++++++++ 1 file changed, 34 insertions(+)