| Message ID | 1649863277-31615-2-git-send-email-quic_srivasam@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add soundcard support for sc7280 based platforms. | expand |
On Wed, Apr 13, 2022 at 08:51:14PM +0530, Srinivasa Rao Mandadapu wrote: > SC7280 has VA, TX and RX macros with SoundWire Controllers to attach with > external codecs using soundwire masters. Add these nodes for sc7280 based > platforms audio use case. > > Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> > Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> > Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 122 +++++++++++++++++++++++++++++++++++ > 1 file changed, 122 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 50fea0e..c0f127f 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -1980,6 +1980,128 @@ > #clock-cells = <1>; > }; > > + lpass_rx_macro: codec@3200000 { > + compatible = "qcom,sc7280-lpass-rx-macro"; > + reg = <0 0x03200000 0 0x1000>; > + > + status = "disabled"; nit: this is easily missed here inmidst of the other stuff, best place it at the end of the node as many other nodes do. > + pinctrl-names = "default"; > + pinctrl-0 = <&lpass_rx_swr>; > + > + clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, > + <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, > + <&lpass_va_macro>; > + clock-names = "mclk", "npl", "fsgen"; > + > + power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, > + <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; > + power-domain-names ="macro", "dcodec"; add space after '='. > + > + #clock-cells = <0>; > + #sound-dai-cells = <1>; > + }; > + > + swr0: soundwire@3210000 { > + compatible = "qcom,soundwire-v1.6.0"; > + reg = <0 0x03210000 0 0x2000>; > + > + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&lpass_rx_macro>; > + clock-names = "iface"; > + > + qcom,din-ports = <0>; > + qcom,dout-ports = <5>; > + > + resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; > + reset-names = "swr_audio_cgcr"; The resets aren't mentioned in the binding, should they be added? > + > + qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; > + qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; > + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; > + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; > + qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; > + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; > + qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; > + qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; > + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; > + > + #sound-dai-cells = <1>; > + #address-cells = <2>; > + #size-cells = <0>; in difference to the other nodes the soundwire ones don't have 'status = "disabled"', should they be disabled by default? > + }; > + > + lpass_tx_macro: codec@3220000 { > + compatible = "qcom,sc7280-lpass-tx-macro"; > + reg = <0 0x03220000 0 0x1000>; > + > + status = "disabled"; > + pinctrl-names = "default"; > + pinctrl-0 = <&lpass_tx_swr>; > + > + clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, > + <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, > + <&lpass_va_macro>; > + clock-names = "mclk", "npl", "fsgen"; > + > + power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, > + <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; > + power-domain-names ="macro", "dcodec"; add space after '=' > + > + #clock-cells = <0>; > + #sound-dai-cells = <1>; > + }; > + > + swr1: soundwire@3230000 { > + compatible = "qcom,soundwire-v1.6.0"; > + reg = <0 0x03230000 0 0x2000>; > + > + interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "swr_master_irq", "swr_wake_irq"; From the binding - interrupt-names: Usage: Optional Value type: boolean Value type: <stringlist> Definition: should be "core" for core and "wakeup" for wake interrupt. Does the binding need an update? > + clocks = <&lpass_tx_macro>; > + clock-names = "iface"; > + > + qcom,din-ports = <3>; > + qcom,dout-ports = <0>; > + > + resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; > + reset-names = "swr_audio_cgcr"; > + > + qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; > + qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; > + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; > + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; > + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; > + qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; > + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; > + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; > + qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; > + qcom,port-offset = <1>; > + > + #sound-dai-cells = <1>; > + #address-cells = <2>; > + #size-cells = <0>; > + }; > + > + lpass_va_macro: codec@3370000 { > + compatible = "qcom,sc7280-lpass-va-macro"; > + reg = <0 0x03370000 0 0x1000>; > + > + status = "disabled"; > + pinctrl-0 = <&lpass_dmic01>; > + pinctrl-names = "default"; > + > + clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; > + clock-names = "mclk"; > + > + power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, > + <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; > + power-domain-names ="macro", "dcodec"; add space after '='. > + > + #clock-cells = <0>; > + #sound-dai-cells = <1>; > + }; > + > lpass_ag_noc: interconnect@3c40000 { > reg = <0 0x03c40000 0 0xf080>; > compatible = "qcom,sc7280-lpass-ag-noc"; > -- > 2.7.4 >
On 4/14/2022 12:24 AM, Matthias Kaehlcke wrote: Thanks for your time Matthias!!! > On Wed, Apr 13, 2022 at 08:51:14PM +0530, Srinivasa Rao Mandadapu wrote: >> SC7280 has VA, TX and RX macros with SoundWire Controllers to attach with >> external codecs using soundwire masters. Add these nodes for sc7280 based >> platforms audio use case. >> >> Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> >> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> >> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 122 +++++++++++++++++++++++++++++++++++ >> 1 file changed, 122 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index 50fea0e..c0f127f 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -1980,6 +1980,128 @@ >> #clock-cells = <1>; >> }; >> >> + lpass_rx_macro: codec@3200000 { >> + compatible = "qcom,sc7280-lpass-rx-macro"; >> + reg = <0 0x03200000 0 0x1000>; >> + >> + status = "disabled"; > nit: this is easily missed here inmidst of the other stuff, best place > it at the end of the node as many other nodes do. Okay. will place accordingly. > >> + pinctrl-names = "default"; >> + pinctrl-0 = <&lpass_rx_swr>; >> + >> + clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, >> + <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, >> + <&lpass_va_macro>; >> + clock-names = "mclk", "npl", "fsgen"; >> + >> + power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,p >> + <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; >> + power-domain-names ="macro", "dcodec"; > add space after '='. Okay. > >> + >> + #clock-cells = <0>; >> + #sound-dai-cells = <1>; >> + }; >> + >> + swr0: soundwire@3210000 { >> + compatible = "qcom,soundwire-v1.6.0"; >> + reg = <0 0x03210000 0 0x2000>; >> + >> + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&lpass_rx_macro>; >> + clock-names = "iface"; >> + >> + qcom,din-ports = <0>; >> + qcom,dout-ports = <5>; >> + >> + resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; >> + reset-names = "swr_audio_cgcr"; > The resets aren't mentioned in the binding, should they be added? Yes. They are to be added. Mentioned same in the cover letter dependencies. > >> + >> + qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; >> + qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; >> + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; >> + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; >> + qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; >> + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; >> + qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; >> + qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; >> + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; >> + >> + #sound-dai-cells = <1>; >> + #address-cells = <2>; >> + #size-cells = <0>; > in difference to the other nodes the soundwire ones don't have > 'status = "disabled"', should they be disabled by default? Okay. will add accordingly. > >> + }; >> + >> + lpass_tx_macro: codec@3220000 { >> + compatible = "qcom,sc7280-lpass-tx-macro"; >> + reg = <0 0x03220000 0 0x1000>; >> + >> + status = "disabled"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&lpass_tx_swr>; >> + >> + clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, >> + <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, >> + <&lpass_va_macro>; >> + clock-names = "mclk", "npl", "fsgen"; >> + >> + power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, >> + <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; >> + power-domain-names ="macro", "dcodec"; > add space after '=' Okay. > >> + >> + #clock-cells = <0>; >> + #sound-dai-cells = <1>; >> + }; >> + >> + swr1: soundwire@3230000 { >> + compatible = "qcom,soundwire-v1.6.0"; >> + reg = <0 0x03230000 0 0x2000>; >> + >> + interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, >> + <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "swr_master_irq", "swr_wake_irq"; > From the binding > > - interrupt-names: > Usage: Optional > Value type: boolean > Value type: <stringlist> > Definition: should be "core" for core and "wakeup" for wake interrupt. > > Does the binding need an update? Here interrupt names are not being used. Will remove here. > >> + clocks = <&lpass_tx_macro>; >> + clock-names = "iface"; >> + >> + qcom,din-ports = <3>; >> + qcom,dout-ports = <0>; >> + >> + resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; >> + reset-names = "swr_audio_cgcr"; >> + >> + qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; >> + qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; >> + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; >> + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; >> + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; >> + qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; >> + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; >> + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; >> + qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; >> + qcom,port-offset = <1>; >> + >> + #sound-dai-cells = <1>; >> + #address-cells = <2>; >> + #size-cells = <0>; >> + }; >> + >> + lpass_va_macro: codec@3370000 { >> + compatible = "qcom,sc7280-lpass-va-macro"; >> + reg = <0 0x03370000 0 0x1000>; >> + >> + status = "disabled"; >> + pinctrl-0 = <&lpass_dmic01>; >> + pinctrl-names = "default"; >> + >> + clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; >> + clock-names = "mclk"; >> + >> + power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, >> + <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; >> + power-domain-names ="macro", "dcodec"; > add space after '='. Okay. > >> + >> + #clock-cells = <0>; >> + #sound-dai-cells = <1>; >> + }; >> + >> lpass_ag_noc: interconnect@3c40000 { >> reg = <0 0x03c40000 0 0xf080>; >> compatible = "qcom,sc7280-lpass-ag-noc"; >> -- >> 2.7.4 >>
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 50fea0e..c0f127f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1980,6 +1980,128 @@ #clock-cells = <1>; }; + lpass_rx_macro: codec@3200000 { + compatible = "qcom,sc7280-lpass-rx-macro"; + reg = <0 0x03200000 0 0x1000>; + + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&lpass_rx_swr>; + + clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, + <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, + <&lpass_va_macro>; + clock-names = "mclk", "npl", "fsgen"; + + power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, + <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; + power-domain-names ="macro", "dcodec"; + + #clock-cells = <0>; + #sound-dai-cells = <1>; + }; + + swr0: soundwire@3210000 { + compatible = "qcom,soundwire-v1.6.0"; + reg = <0 0x03210000 0 0x2000>; + + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&lpass_rx_macro>; + clock-names = "iface"; + + qcom,din-ports = <0>; + qcom,dout-ports = <5>; + + resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; + reset-names = "swr_audio_cgcr"; + + qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; + qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; + qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; + qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; + + #sound-dai-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; + }; + + lpass_tx_macro: codec@3220000 { + compatible = "qcom,sc7280-lpass-tx-macro"; + reg = <0 0x03220000 0 0x1000>; + + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&lpass_tx_swr>; + + clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, + <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, + <&lpass_va_macro>; + clock-names = "mclk", "npl", "fsgen"; + + power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, + <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; + power-domain-names ="macro", "dcodec"; + + #clock-cells = <0>; + #sound-dai-cells = <1>; + }; + + swr1: soundwire@3230000 { + compatible = "qcom,soundwire-v1.6.0"; + reg = <0 0x03230000 0 0x2000>; + + interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "swr_master_irq", "swr_wake_irq"; + clocks = <&lpass_tx_macro>; + clock-names = "iface"; + + qcom,din-ports = <3>; + qcom,dout-ports = <0>; + + resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; + reset-names = "swr_audio_cgcr"; + + qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; + qcom,port-offset = <1>; + + #sound-dai-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; + }; + + lpass_va_macro: codec@3370000 { + compatible = "qcom,sc7280-lpass-va-macro"; + reg = <0 0x03370000 0 0x1000>; + + status = "disabled"; + pinctrl-0 = <&lpass_dmic01>; + pinctrl-names = "default"; + + clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; + clock-names = "mclk"; + + power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, + <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; + power-domain-names ="macro", "dcodec"; + + #clock-cells = <0>; + #sound-dai-cells = <1>; + }; + lpass_ag_noc: interconnect@3c40000 { reg = <0 0x03c40000 0 0xf080>; compatible = "qcom,sc7280-lpass-ag-noc";